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在多级缓存上缓存未命中

[英]Cache miss on a multilevel cache

原文 2015-04-29 15:53:09 1 1 caching

There are 2 levels of cache L1 and L2. 缓存L1和L2有2个级别。 If there is a cache miss on both levels, data is being read from the memory. 如果两个级别上都有高速缓存未命中，则正在从内存中读取数据。 During reading the data from main memory, will the data be first entered into L2 and L1 cache first and then the processor reads the data from L1 cache or the updation into L1 and L2 and the read to processor happen simultaneously? 从主存储器读取数据期间，是否将数据首先首先输入到L2和L1高速缓存中，然后处理器从L1高速缓存中读取数据，或者将数据更新到L1和L2，并且同时读取到处理器？

1 个解决方案

I believe this depends on the hardware implementation. 我相信这取决于硬件的实现。 I think it also depends on whether or not it is a write-through or write-back cache. 我认为这还取决于它是直写式缓存还是回写式缓存。 A write through would have the same data at all levels because it updates it all at the same time. 直写在所有级别上都具有相同的数据，因为它可以同时更新所有数据。 It could also be put into a write buffer to be written into the cache, in which case it would happen at the same time as the read. 也可以将其放入写入缓冲区以写入高速缓存，在这种情况下，它将与读取同时发生。 If there was no write buffer, the processor might stall to allow the cache to be updated. 如果没有写缓冲区，则处理器可能会停顿以允许更新缓存。