如何在VHDL中实现链接列表？

Question

Is it possible to create linked lists in VHDL? (ex. read the file at zero time and load all the values into it?)

Answer 1

I think it is possible. Not only as an static list as mentioned in the comments but also dynamic. My solution would go along the lines of using a RAM (most likely Block RAM, but this is really architecture depended) and storing there the required data along with a pointer to the next item and a valid bit (optional) and "last" flag. It would look something like:

                     RAM 
  Addr0   -> | Valid0 & Last0 & Data0 & Pointer0 |
  Addr1   -> | Valid1 & Last1 & Data1 & Pointer1 |
               ...
  AddrN   -> | ValidN & LastN & DataN & PointerN |

So, for example, after initialization, assuming some random data and that the linked list have been loaded in order with N values (and a not circular list), it may look like:

                        RAM 
                        V   L   Data     Pointer
  Addr0(0000000)   -> | 1 & 0 & XXXXXX & 0000001 |
  Addr1(0000001)   -> | 1 & 0 & YYYYYY & 0000010 |
                       ...
  AddrN(xxxxxx0)   -> | 1 & 1 & ZZZZZZ & 0000000 |

After this, the contents of the RAM can be altered as required. For example, to "delete" element 1 ( in addr = Addr1), the Pointer0 and Valid1 should be changed:

                        RAM 
                        V   L   Data     Pointer
  Addr0(0000000)   -> | 1 & 0 & XXXXXX & 0000010 |
  Addr1(0000001)   -> | 0 & 0 & YYYYYY & 0000010 |
  Addr1(0000010)   -> | 1 & 0 & MMMMMM & 0000011 |
               ...
  AddrN(xxxxxx0)   -> | 1 & 1 & ZZZZZZ & 0000000 |

Or adding an element between element0 and element1:

                        RAM 
                        V   L   Data     Pointer
  Addr0(0000000)   -> | 1 & 0 & XXXXXX & xxxxxx1 |
  Addr1(0000001)   -> | 1 & 0 & YYYYYY & 0000010 |
  Addr1(0000010)   -> | 1 & 0 & MMMMMM & 0000011 |
               ...
  AddrN(xxxxxx0)   -> | 1 & 1 & ZZZZZZ & 0000000 |
  AddrN(xxxxxx1)   -> | 1 & 0 & ZZZZZZ & 0000001 |

Again, this is only an idea and several improvements could be made. One of such would be to use record types instead of concatenating for ease of use ( you would have to transform it to a normal std_logic_vector if you are using a block Ram, but this is architecture depended).

Good Luck!