如何在 ARM 或 THUMB 模式下写入 function 以读取 ARM CPSR？

Question

I am working on an ARMv7 (Cortex-A7) system, and I want to read CPSR from C file in either ARM mode or THUMB mode.

Firstly, I used the embedded ASSEMBLY instruction in C function as follows,

 __asm__ volatile("mrs %0, CPSR\n" : "=r"(regval));

When I compiled the C file with -mthumb and ran the code with GDB, it showed that the regval is 0x60000010 which is NOT the 0x60000030 shown by GDB!

So how to write a function to read CPSR in either ARM or THUMB mode?

Updated with compiling option

a) Build the code with following command line to specify the THUMB mode.
arm-linux-gnueabi-gcc -g2 backtrace.c -mcpu=cortex-a7 -static -mthumb -o tbacktrace Run tbacktrace with qemu and GDB, I got different value as,

(gdb) p/x regval
$7 = 0x60000010
(gdb) p/x $cpsr
$8 = 0x60000030

The question is why my mrs %0, CPSR\n showd CPSR is ARM mode, instead of THUMB mode which the code is built.

b) When build the code with command line (not specify -mcpu=cortex-a7),

arm-linux-gnueabi-gcc -g2 backtrace.c -mthumb -o tbacktrace

there reported the following error.

$ arm-linux-gnueabi-gcc -g2 backtrace.c -mthumb -o tbacktrace
/tmp/ccOg2tlo.s: Assembler messages:
/tmp/ccOg2tlo.s:2256: Error: selected processor does not support `mrs r3,CPSR' in Thumb mode
/tmp/ccOg2tlo.s:2398: Error: selected processor does not support `mrs r3,CPSR' in Thumb mode

c) Build the code without -mcpu or -mthumb, the code can be built and ran well. So I think there should be some other ways to get right CPSR in both ARM and THUMB modes.

Answer 1

CPSR.c :

#include <stdint.h>

int main(int argc, char* argv[]) {
  uint32_t regval;
  asm volatile("mrs %0, CPSR" : "=r"(regval));
  return regval;
}

If you don't use -mcpu=cortex-a7 , your compiler will default to another CPU:

/opt/arm/10/gcc-arm-none-eabi-10.3-2021.10/bin/arm-none-eabi-gcc -O0 -nostartfiles -nostdlib -Wl,--section-start=.text=0x80800000 -S CPSR.c

cat CPSR.s 
        .cpu arm7tdmi
        .arch armv4t

    

The ARM7TDMI-S was introduced in 2001, and, as pointed out by your compiler, does not seem to support does not support mrs r3,CPSR in Thumb mode. Therefore, you must specify -mcpu=cortex-a7 :

/opt/arm/10/gcc-arm-none-eabi-10.3-2021.10/bin/arm-none-eabi-gcc -mcpu=cortex-a7 -O0 -nostartfiles -nostdlib -Wl,--section-start=.text=0x80800000 -S CPSR.c

cat CPSR.s 
       .cpu cortex-a7
       .arch armv7-a

CPU and architecture are now as expected.

Testing your code on real hardware - a Cortex-A7 running u-boot - in Arm and Thumb mode:

Arm:

/opt/arm/10/gcc-arm-none-eabi-10.3-2021.10/bin/arm-none-eabi-gcc -O0 -mcpu=cortex-a7 -marm -nostartfiles -nostdlib -Wl,--section-start=.text=0x80800000 -o CPSR-arm.elf CPSR.c
/opt/arm/10/gcc-arm-none-eabi-10.3-2021.10/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/bin/ld: warning: cannot find entry symbol _start; defaulting to 0000000080800000
/opt/arm/10/gcc-arm-none-eabi-10.3-2021.10/bin/arm-none-eabi-objcopy -O srec CPSR-arm.elf CPSR-arm.srec
/opt/arm/10/gcc-arm-none-eabi-10.3-2021.10/bin/arm-none-eabi-objdump -j .text -D CPSR-arm.elf

CPSR-arm.elf:     file format elf32-littlearm


Disassembly of section .text:

80800000 <main>:
80800000:       e52db004        push    {fp}            ; (str fp, [sp, #-4]!)
80800004:       e28db000        add     fp, sp, #0
80800008:       e24dd01c        sub     sp, sp, #28
8080000c:       e50b0010        str     r0, [fp, #-16]
80800010:       e50b1014        str     r1, [fp, #-20]  ; 0xffffffec
80800014:       e50b2018        str     r2, [fp, #-24]  ; 0xffffffe8
80800018:       e10f3000        mrs     r3, CPSR
8080001c:       e50b3008        str     r3, [fp, #-8]
80800020:       e51b3008        ldr     r3, [fp, #-8]
80800024:       e1a00003        mov     r0, r3
80800028:       e28bd000        add     sp, fp, #0
8080002c:       e49db004        pop     {fp}            ; (ldr fp, [sp], #4)
80800030:       e12fff1e        bx      lr

I.MX7d running u-boot:

# loads
## Ready for S-Record download ...

## First Load Addr = 0x80800000
## Last  Load Addr = 0x80800033
## Total Size      = 0x00000034 = 52 Bytes
CACHE: Misaligned operation at range [80800000, 80800034]
## Start Addr      = 0x80800000
# go 0x80800000
## Starting application at 0x80800000 ...
## Application terminated, rc = 0x200000D3

Thumb:

/opt/arm/10/gcc-arm-none-eabi-10.3-2021.10/bin/arm-none-eabi-gcc -O0 -mcpu=cortex-a7 -mthumb -nostartfiles -nostdlib -Wl,--section-start=.text=0x80800000 -o CPSR-thumb.elf CPSR.c
/opt/arm/10/gcc-arm-none-eabi-10.3-2021.10/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/bin/ld: warning: cannot find entry symbol _start; defaulting to 0000000080800000
/opt/arm/10/gcc-arm-none-eabi-10.3-2021.10/bin/arm-none-eabi-objcopy -O srec CPSR-thumb.elf CPSR-thumb.srec
/opt/arm/10/gcc-arm-none-eabi-10.3-2021.10/bin/arm-none-eabi-objdump -j .text -D CPSR-thumb.elf

CPSR-thumb.elf:     file format elf32-littlearm


Disassembly of section .text:

80800000 <main>:
80800000:       b480            push    {r7}
80800002:       b087            sub     sp, #28
80800004:       af00            add     r7, sp, #0
80800006:       60f8            str     r0, [r7, #12]
80800008:       60b9            str     r1, [r7, #8]
8080000a:       607a            str     r2, [r7, #4]
8080000c:       f3ef 8300       mrs     r3, CPSR
80800010:       617b            str     r3, [r7, #20]
80800012:       697b            ldr     r3, [r7, #20]
80800014:       4618            mov     r0, r3
80800016:       371c            adds    r7, #28
80800018:       46bd            mov     sp, r7
8080001a:       bc80            pop     {r7}
8080001c:       4770            bx      lr

I.MX7d running u-boot:

# loads
## Ready for S-Record download ...

## First Load Addr = 0x80800000
## Last  Load Addr = 0x8080001D
## Total Size      = 0x0000001E = 30 Bytes
CACHE: Misaligned operation at range [80800000, 8080001e]
## Start Addr      = 0x80800000
# 
# go 0x80800001
## Starting application at 0x80800001 ...
## Application terminated, rc = 0x200000D3

Bottom-line, both versions returned the same value for CPSR, ie 0x200000D3 .

To the question

How to write a function to read ARM CPSR in either ARM or THUMB mode?

The answer would then be: The way you did. Asking why p/x regval and p/x $cpsr are not returning the same value should be the topic for a different question, may be on the GDB forum.

Answer 2

The instruction is working as designed and documented.

The discrepancy is in bit 5, which according to the ARMv7-A Architecture Reference Manual , is the T bit, indicating whether the processor is in Thumb state. It's one of the "execution state bits". Lower down on that page, under "Accessing the execution state bits", it says:

The execution state bits, other than the E bit, are RAZ [read as zero] when read by an MRS instruction.

So mrs rN, CPSR masks off those bits. I'm not sure why it's designed this way. But in principle you should already know whether you're in Thumb state or not, so it shouldn't really be necessary to read this information from CPSR.

On the other hand, gdb doesn't get its CPSR value from mrs rN, CPSR . I haven't checked, but I presume what happens is this: when your program hits a breakpoint, an exception is generated. This causes CPSR to be saved into SPSR (without masking any bits,), and the kernel's exception handler retrieves it from there to store as part of the saved context of your process, along with register values. etc. The saved context is made available to the debugger via appropriate system calls (eg ptrace(2) ) and that's how it is able to display register contents and such. In particular, it gets the CPSR value that was saved at the breakpoint and which isn't masked.