Cache miss on a multilevel cache

Question

There are 2 levels of cache L1 and L2. If there is a cache miss on both levels, data is being read from the memory. During reading the data from main memory, will the data be first entered into L2 and L1 cache first and then the processor reads the data from L1 cache or the updation into L1 and L2 and the read to processor happen simultaneously?

Answer 1

I believe this depends on the hardware implementation. I think it also depends on whether or not it is a write-through or write-back cache. A write through would have the same data at all levels because it updates it all at the same time. It could also be put into a write buffer to be written into the cache, in which case it would happen at the same time as the read. If there was no write buffer, the processor might stall to allow the cache to be updated.