我的 VHDL 代码中的语法错误在哪里？

Question

我正在用 vhdl 编写方波发生器，我只是很困惑为什么在我的 LUT 声明中出现语法错误（第 21 行）。 我花了几个小时试图通过注释掉某些片段并包含不同的东西来找出我的错误，但它总是相同的错误。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

entity highlow_square is
   PORT ( clk    : in  STD_LOGIC; -- clock to be divided
           reset  : in  STD_LOGIC; -- active-high reset
           enable : in  STD_LOGIC; -- active-high enable
           Ampselect : in STD_LOGIC_VECTOR(3 DOWNTO 0);

                                   -- useful to enable another device, like to slow down a counter
           value  : out STD_LOGIC_VECTOR (9 downto 0) -- outputs the current_count value, if needed
         );
end highlow_square;

architecture Behavioral of highlow_square is
signal duty_cycle_sig : std_logic_vector (9 downto 0);
signal current_count : std_logic_vector(9 downto 0);
signal check : integer := 0;  
type array_1d is array (0 to 15) of integer;
constant DutyCycle_LUT : array_1d := (‭ 
(   1023    )   ,
(   960 )   ,
(   897 )   ,
(   834 )   ,
(   771 )   ,
(   708 )   ,
(   645 )   ,
(   582 )   ,
(   519 )   ,
(   456 )   ,
(   393 )   ,
(   330 )   ,
(   267 )   ,
(   204 )   ,
(   141 )   ,
(   78      )       
);


begin

duty_cycle_sig <= std_logic_vector(to_unsigned(DutyCycle_LUT(to_integer(unsigned(Ampselect))),duty_cycle_sig'length));


   count: process(clk,reset,check,enable)

    begin 
       if (reset = '1') then 
          current_count <= "0000000000" ;

       elsif (rising_edge(clk)) then 
        if(enable = '1') then
            if(check = 0) then
                if(current_count < "1111111110") then
                current_count <= current_count + "10";
                value <= duty_cycle_sig;
                end if;

                if(current_count = "1111111100") then
                check <= 1;
                end if;

            else
                if(current_count > "000000000") then
                current_count <= current_count - "10";
                value <= "0000000000";
                end if;

                if(current_count = "0000000010") then
                check <= 0;
                end if;


        end if;
    end if;
    end if;      
  end process;



END Behavioral;

我收到以下错误

Error (10500): VHDL syntax error at highlow_square.vhdl(21) near text 
Error (10500): VHDL syntax error at highlow_square.vhdl(21) near text "";  expecting ")", or ","
Error (10500): VHDL syntax error at highlow_square.vhdl(21) near text ­
Error (10500): VHDL syntax error at highlow_square.vhdl(47) near text ")";  expecting ":", or ","

我不知道我在 LUT 声明中或之前在哪里犯了错误。 非常感谢您的帮助！