错误 (10558)：keypad.vhd(53) 处的 VHDL 错误：无法将模式“out”的正式端口“代码”与表达式相关联

Question

错误 (10482)：keypad.vhd(53) 处的 VHDL 错误：object “代码”已使用但未声明

错误 (10558)：keypad.vhd(53) 处的 VHDL 错误：无法将模式“out”的正式端口“代码”与表达式相关联

首先，对不起我的英语不好。（）

我正在制作一个由 keypad.vhd & keypad_scan.vhd & d_7seg.vhd keypad_scan.vhd 组成的程序，它正在继续扫描键盘。 d_7seg.vhd 仅显示四个 7 段的数字。 然后 keypad.vhd 是一个主要部分，就像我按下按钮（0~9）时一样，数字显示在 LSB 7 段上，将前一个数字推到左边。

我不明白为什么它不起作用。 这是我的代码。

keypad.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity keypad is
    port( clk_1k : in std_logic;
            col : in std_logic_vector(2 downto 0);
            row : out std_logic_vector(3 downto 0);
            seg_com : out std_logic_vector(3 downto 0);
            seg_data : out std_logic_vector(7 downto 0));
end keypad;

architecture input_keypad_arch of keypad is

    component keypad_scan is
        port( clk_1k : in std_logic;
                col : in std_logic_vector(2 downto 0);
                row : buffer std_logic_vector(3 downto 0);
                strobe : out std_logic;
                code : out std_logic_vector(3 downto 0));    <--- 'code' is a troublemaker....
    end component;
    
    component d_7seg is
        port( clk : in std_logic;
                d0 : in integer range 0 to 9;
                d1 : in integer range 0 to 9;
                d2 : in integer range 0 to 9;
                d3 : in integer range 0 to 9;
                seg_com : out std_logic_vector(3 downto 0);
                seg_data : out std_logic_vector(7 downto 0));
    end component;
    
    signal key : std_logic_vector(3 downto 0);
    signal d0, d1, d2, d3 : integer range 0 to 9;
    signal strobe : std_logic;
    
begin
    p_shift : process(strobe, key)
    begin
        if(key = "1010" or key = "1011") then
            d0 <= 0;
            d1 <= 0;
            d2 <= 0;
            d3 <= 0;
        elsif strobe'event and strobe = '1' then
            d3 <= d2;
            d2 <= d1;
            d1 <= d0;
            d0 <= conv_integer(key);
        end if;
    end process;
    
    keyin : keypad_scan port map(clk_1k, col, row, strobe, code);
    disp : d_7seg port map(clk, d0, d1, d2, d3, seg_com, seg_data);
end input_keypad_arch;

keypad_scan.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity keypad_scan is
    port( clk_1k : in std_logic;
            col : in std_logic_vector(2 downto 0);
            row : buffer std_logic_vector(3 downto 0);
            strobe : out std_logic;
            code : out std_logic_Vector(3 downto 0));
end keypad_scan;

architecture keypad_scan_arch of keypad_scan is
    signal scan : integer range 0 to 3;
    signal k : std_logic_vector(0 to 11);
    signal t1 : std_logic;
    
begin
    p_scan : process(clk_1k)
    begin
        if clk_1k'event and clk_1k = '1' then
            if scan /= 3 then
                scan <= scan + 1;
            else
                scan <= 0;
            end if;
        end if;
    end process;
    
    p_row : process(clk_1k, scan)
    begin
        if clk_1k'event and clk_1k = '1' then
            case scan is 
                when 0 => row <= "0001";
                when 1 => row <= "0010";
                when 2 => row <= "0100";
                when 3 => row <= "1000";
            end case;
        end if;
    end process;
    
    p_r0 : process(clk_1k, row)
    begin
        if clk_1k'event and clk_1k = '1' and row = "0001" then
            k(1) <= col(0);
            k(2) <= col(1);
            k(3) <= col(2);
        end if;
    end process;
    
    p_r1 : process(clk_1k, row)
    begin
        if clk_1k'event and clk_1k = '1' and row = "0010" then
            k(4) <= col(0);
            k(5) <= col(1);
            k(6) <= col(2);
        end if;
    end process;
    
    p_r2 : process(clk_1k, row)
    begin
        if clk_1k'event and clk_1k = '1' and row = "0100" then
            k(7) <= col(0);
            k(8) <= col(1);
            k(9) <= col(2);
        end if;
    end process;
    
    p_r3 : process(clk_1k, row)
    begin
        if clk_1k'event and clk_1k = '1' and row = "1000" then
            k(10) <= col(0);
            k(0) <= col(1);
            k(11) <= col(2);
            
        end if;
    end process;
    
    p_stb : process(clk_1k, k, t1)
        variable sin : std_logic;
    begin
        sin := not (k(0) or k(1) or k(2) or k(3) or k(4) or k(5) or k(6) or k(7) or k(8) or k(9) or k(10) or k(11));
        if clk_1k'event and clk_1k = '1' then
            t1 <= sin;
        end if;
        strobe <= sin or (not t1);
    end process;
    
    p_enc : process(k)
    begin
        if k(11) = '1' then code <= "1011";
        elsif k(10) = '1' then code <= "1010";
        elsif k(9) = '1' then code <= "1001";
        elsif k(8) = '1' then code <= "1000";
        elsif k(7) = '1' then code <= "0111";
        elsif k(6) = '1' then code <= "0110";
        elsif k(5) = '1' then code <= "0101";
        elsif k(4) = '1' then code <= "0100";
        elsif k(3) = '1' then code <= "0011";
        elsif k(2) = '1' then code <= "0010";
        elsif k(1) = '1' then code <= "0001";
        elsif k(0) = '1' then code <= "0000";
        else code <= "1111";
        end if;
    end process;
end keypad_scan_arch;

d_7seg.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity d_7seg is
    port( clk : in std_logic;
            d0 : in integer range 0 to 9;
            d1 : in integer range 0 to 9;
            d2 : in integer range 0 to 9;
            d3 : in integer range 0 to 9;
            seg_com : out std_logic_vector(3 downto 0);
            seg_data : out std_logic_vector(7 downto 0));
end d_7seg;

architecture d_7seg_arch of d_7seg is
    signal scan : integer range 0 to 3 := 0;
    
        function dec_7_seg(bcd : integer range 0 to 9) return std_logic_vector is
            variable res : std_logic_vector(7 downto 0);
            
        begin
            if(bcd = "0000") then res := "00111111";
            elsif(bcd = "0001") then res := "00000110";
            elsif(bcd = "0010") then res := "01011011";
            elsif(bcd = "0011") then res := "01001111";
            elsif(bcd = "0100") then res := "01100110";
            elsif(bcd = "0101") then res := "01101101";
            elsif(bcd = "0110") then res := "01111101";
            elsif(bcd = "0111") then res := "00100111";
            elsif(bcd = "1000") then res := "01111111";
            elsif(bcd = "1001") then res := "01100111";
            else res := "11000000";
            end if;
            return res;
        end dec_7_seg;
        
begin
    p_scan : process(clk)
    begin
        if clk'event and clk = '1' then
            if scan /= 3 then
                scan <= scan + 1;
            else
                scan <= 0;
            end if;
        end if;
    end process;
    
    p_disp : process(scan, d0, d1, d2, d3)
    begin
        case scan is
            when 0 => 
                seg_data <= dec_7_seg(d0);
                seg_com <= "1110";
            when 1 => 
                seg_data <= dec_7_seg(d1);
                seg_com <= "1101";
            when 2 => 
                seg_data <= dec_7_seg(d2);
                seg_com <= "1011";
            when 3 =>
                seg_data <= dec_7_seg(d3);
                seg_com <= "0111";
            when others =>
                seg_data <= x"00";
                seg_com <= "1111";
        end case;
    end process;
end d_7seg_arch;

如果您需要更多详细信息，请写评论。 我很抱歉我的英语不好。