嗨，我正在尝试使用Verilog实现硬件的5级流水线16 * 16位矩阵乘法

Question

`include "define.v"
module matmult_kernel (Clk, Start, A_0, A_1, A_2, A_3, A_4, A_5, A_6, A_7,
                   A_8, A_9, A_10, A_11, A_12, A_13, A_14, A_15,
                   B_0, B_1, B_2, B_3, B_4, B_5, B_6, B_7,
                   B_8, B_9, B_10, B_11, B_12, B_13, B_14, B_15,
                   C, Rd_en, Rd_A_addr, Rd_B_addr, Wr_en, Wr_addr
);

input Clk, Start;
input signed [`INPUTWIDTH-1:0] A_0, A_1, A_2, A_3, A_4, A_5, A_6, A_7;
input signed [`INPUTWIDTH-1:0] A_8, A_9, A_10, A_11, A_12, A_13, A_14, A_15;
input signed [`INPUTWIDTH-1:0] B_0, B_1, B_2, B_3, B_4, B_5, B_6, B_7;
input signed [`INPUTWIDTH-1:0] B_8, B_9, B_10, B_11, B_12, B_13, B_14, B_15;

output reg Rd_en, Wr_en;
output reg [`INADDRWIDTH-1:0] Rd_A_addr;
output reg [`INADDRWIDTH-1:0] Rd_B_addr;
output reg [`OUTADDRWIDTH-1:0] Wr_addr;
output [`OUTPUTWIDTH-1:0] C;

//######################################################
reg [8:0] cycle_cnt=`EXECYCLE;
reg [15:0] C_0, C_1, C_2, C_3, C_4, C_5, C_6, C_7, C_8, C_9, C_10, C_11, C_12, C_13, C_14, C_15;
reg [15:0] D_0, D_1, D_2, D_3, D_4, D_5, D_6, D_7;
reg [15:0] E_0, E_1, E_2, E_3;
reg [15:0] F_0, F_1;
reg [15:0] G_0;

always @(posedge Clk)
begin
    if(Start && cycle_cnt == `EXECYCLE) 
    begin
        cycle_cnt<=0;
    end
    else if(cycle_cnt<`EXECYCLE)
    begin
        cycle_cnt<=cycle_cnt+1;
    end
end

always @(posedge Clk)
begin
    //To do: generate signals: Rd_A_addr, Rd_B_addr and Rd_en  
    //Tips: you should use cycle_cnt 

end

always @(posedge Clk)
begin
    if(cycle_cnt>=6 && cycle_cnt<`EXECYCLE)
    begin
        Wr_en<=1;
        Wr_addr<=cycle_cnt-6;
    end
    else 
    begin
        Wr_en<=0;
        Wr_addr<=0;
    end
end

//######################################################
reg [`OUTPUTWIDTH-1:0] reg_state_1 [15:0];
reg [`OUTPUTWIDTH-1:0] reg_state_2 [7:0];
reg [`OUTPUTWIDTH-1:0] reg_state_3 [3:0];
reg [`OUTPUTWIDTH-1:0] reg_state_4 [1:0];
reg [`OUTPUTWIDTH-1:0] reg_state_5;

//state_1
always@(posedge Clk)
begin   
    //To do: finish pipeline stage 1
     C_0=A_0*B_0;
     C_1=A_1*B_1;
     C_2=A_2*B_2;
     C_3=A_3*B_3;
     C_4=A_4*B_4;
     C_5=A_5*B_5;
     C_6=A_6*B_6;
     C_7=A_7*B_7;
     C_8=A_8*B_8;
     C_9=A_9*B_9;
     C_10=A_10*B_10;
     C_11=A_11*B_11;
     C_12=A_12*B_12;
     C_13=A_13*B_13;
     C_14=A_14*B_14;
     C_15=A_15*B_15;

    assign reg_state_1={C_0,C_1,C_2,C_3,C_4,C_5,C_6,C_7,C_8,C_9,C_10,C_11,C_12,C_13,C_14,C_15};
end

//state_2
always@(posedge Clk)
begin
    //To do: finish pipeline stage 2
     D_0=C_0+C_1;
     D_1=C_2+C_3;
     D_2=C_4+C_5;
     D_3=C_6+C_7;
     D_4=C_8+C_9;
     D_5=C_10+C_11;
     D_6=C_12+C_13;
     D_7=C_14+C_15;

     assign reg_state_2={D_0,D_1,D_2,D_3,D_4,D_5,D_6,D_7};

end

//state_3
always@(posedge Clk)
begin

    //To do: finish pipeline stage 3
     E_0=D_0+D_1;
     E_1=D_2+D_3;
     E_2=D_4+D_5;
     E_3=D_6+D_7;

    assign reg_state_3={E_0,E_1,E_2,E_3};
end

//state_4
always@(posedge Clk)
begin
    //To do: finish pipeline stage 4
      F_0=E_0+E_1;
     F_1=E_2+E_3;

    assign reg_state_4={F_0,F_1};
end

//state_5
always@(posedge Clk)
begin
     G_0=F_0+F_1;
    //To do: finish pipeline stage 5
    assign reg_state_5=G_0;
end

assign C=reg_state_5;

endmodule

因此，对于所有阶段，我基本上都是在尝试实现这一点，

我知道为什么会出错：1）无法直接分配给内存reg_state_1 2）无法直接分配给内存reg_state_2 3）无法直接分配给内存reg_state_3 4）无法直接分配给内存reg_state_4

另外，我不了解此功能的原因，

always @(posedge Clk)
begin
    //To do: generate signals: Rd_A_addr, Rd_B_addr and Rd_en  
    //Tips: you should use cycle_cnt 

end

感谢您的时间。 非常感激。 对不起，如果prg太大。

Answer 1

1 /在Verilog中，不能使用mem = {....}来分配多个存储位置。

最简单的解决方案是在不使用中间变量（例如C_0，C_1等）的情况下分配给内存：

//To do: finish pipeline stage 1
 reg_state_1[0] <= A_0*B_0;
 reg_state_1[0] <= A_1*B_1;
 // Note my use of `<=` and not `=`. 

2 /作为toolic说摆脱了assign ，但只有里面always部分。 始终必须保持外部分配。

另外，我不了解此功能的原因，

实际上，这是最令人担忧的。 您正在使用根本上很重要的Verilog构造，但不了解您在做什么。 它超出了本论坛的范围，无法解释其功能以及如何使用它。 我建议您先阅读时钟，寄存器，阻塞和非阻塞分配。
在您了解编写任何体面的Verilog代码之前，很可能会筋疲力尽。