运行模拟时，vivado [12-4473]和USF-XSim-62错误消息

Question

Verilog错误；

运行模拟时，vivado [12-4473]和USF-XSim-62错误消息

1. [USF-XSim-62]“编译”步骤失败，并出现错误。 请检查Tcl控制台输出或'C：/Users/Yehanrulzs/Desktop/project_1/project_1.sim/sim_1/behav/xsim/xvlog.log'文件以获取更多信息。

信息是xvlog：

INFO：[VRFC 10-2263]将Verilog文件“ C：/Users/Yehanrulzs/Desktop/project_1/project_1.srcs/sources_1/new/multiplier.v”分析到库xil_defaultlib中INFO：[VRFC 10-311]分析模块乘数INFO ：[VRFC 10-2263]将Verilog文件“ C：/Users/Yehanrulzs/Desktop/project_1/project_1.srcs/sources_1/new/test_bed.v”分析到库xil_defaultlib INFO中：[VRFC 10-311]分析模块test_bed错误： [VRFC 10-1280]不允许将程序分配给非寄存器num1，左侧应为reg / integer / time / genvar [C：/Users/Yehanrulzs/Desktop/project_1/project_1.srcs/sources_1/new /test_bed.v:31]错误：[VRFC 10-1280]不允许将程序分配给非寄存器num2，左侧应为reg / integer / time / genvar [C：/ Users / Yehanrulzs / Desktop / project_1 / project_1.srcs / sources_1 / new / test_bed.v：32]错误：[VRFC 10-1280]不允许将程序分配给非寄存器num2，左侧应为reg / integer / time / genvar [ C：/用户/ Yehanrulzs /桌面/ pro ject_1 / project_1.srcs / sources_1 / new / test_bed.v：35]错误：由于先前的错误，[VRFC 10-2865]模块'test_bed'被忽略了[C：/Users/Yehanrulzs/Desktop/project_1/project_1.srcs/sources_1 /new/test_bed.v:23]

2. [Vivado 12-4473]运行模拟时检测到错误。 请更正问题，然后重试此操作。

下面的代码表示一个16位浮点乘法器及其仿真。鉴于上述两个错误，不会生成仿真结果。

module multiplier(num1,num2,result,overflow);

  input [15:0] num1, num2;
  output [15:0] result;
  output overflow;
  wire sign1, sign2, signr; //hold signs
  wire [4:0] ex1, ex2; //hold exponents
  wire [9:0] fra1, fra2; //hold fractions
  wire [10:0] float1; // true value of fra1 i.e. 1.ffffffffff
  wire [5:0] exSum; //exponent sum
  wire [10:0] float_res; //fraction result
  reg [10:0] mid[9:0], mid2[1:0];


  assign overflow = exSum[5]; //extra digit of final sum exist at overflow
  //decode numbers
  assign {sign1, ex1, fra1} = num1;
  assign {sign2, ex2, fra2} = num2;
  //Same signs give 0 (positive), different signs give 1 (negative)
  assign signr = (sign1 ^ sign2);
  assign exSum = (ex1 + ex2); //exponentials are added
  assign float1 = {1'b1, fra1};
  assign float_res = float1 + mid2[1] + mid2[0]; //add mid2 terms and integer  of num2
  assign result = {signr, exSum[4:0], float_res[9:0]};


  always@* //create mids from fractions
    begin
      mid[0] = (float1 >> 10) & {16{fra2[0]}};
      mid[1] = (float1 >> 9) & {16{fra2[1]}};
      mid[2] = (float1 >> 8) & {16{fra2[2]}};
      mid[3] = (float1 >> 7) & {16{fra2[3]}};
      mid[4] = (float1 >> 6) & {16{fra2[4]}};
      mid[5] = (float1 >> 5) & {16{fra2[5]}};
      mid[6] = (float1 >> 4) & {16{fra2[6]}};
      mid[7] = (float1 >> 3) & {16{fra2[7]}};
      mid[8] = (float1 >> 2) & {16{fra2[8]}};
      mid[9] = (float1 >> 1) & {16{fra2[9]}};
    end


  always@* //create mid2s from mids
    begin
      mid2[1] = mid[0] + mid[1] + mid[2] + mid[3] + mid[4];
      mid2[0] = mid[5] + mid[6] + mid[7] + mid[8] + mid[9];
    end






endmodule

仿真代码如下，

module test_bed();

reg num1,num2;
reg result,overflow;

multiplier multi1 (num1,num2,result,overflow);
    initial
    begin
     num1= 12.25;
     num2= 12.13;


     #2 num2= 15.38;

    end


endmodule

有人可以向我建议代码错误吗？