如何解决verilog的非法引用错误

Question

我不断收到错误消息。 我不知道有什么问题

** 错误：C:/intelFPGA/sample(1)/minute.v(25): (vlog-2110) 非法引用.net“秒”。

这是我的错误信息。

module minute(
    clk,  //Clock with 1 Hz frequency    [Clk_1sec]
    reset,     //active high reset
    seconds,
    minutes);

//What are the Inputs?
    input clk; 
    input reset;
    input seconds;
//What are the Outputs?
    output [5:0] minutes;
 
//Internal variables.
   
    reg [5:0] minutes;
   

   //Execute the always blocks when the Clock or reset inputs are
    //changing from 0 to 1(positive edge of the signal)
    always @(posedge(clk) or posedge(reset))
   
            if(seconds == 6'd60) begin //check for max value of sec
                seconds = 6'd0;  //reset seconds
                minutes = minutes + 2'b1; //increment minutes
               
    end    

endmodule 

Answer 1

seconds是你的输入。 它被驱动到模块minute之外的某个地方。 你不能在这里修改它。

            if(seconds == 6'd60) begin //check for max value of sec
                seconds = 6'd0;  //reset seconds                   // <----- HERE
                minutes = minutes + 2'b1; //increment minutes
               
    end