计数器向量在模拟时显示非二进制 output

Question

我已经过滤掉了很多错误，我的代码现在可以根据测试台正确模拟。 但是问题是，如果您查看 reg_counter 向量的模拟 output ，它会显示非常奇怪的非数字输出，因为它是计数器，所以不应该有。 然而，向量的每个元素都是一个正常的二进制数。 我该如何解决？

代码：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

entity encoder_control is
    Port ( A : in STD_LOGIC;
           A2 : in STD_LOGIC; --inverse signal
           B : in STD_LOGIC;
           B2 : in STD_LOGIC; --inverse signal
           I : in STD_LOGIC;
           I2 : in STD_LOGIC; --inverse signal
           Error : out STD_LOGIC;
           Reset : in STD_LOGIC;
           Sys_clk : in STD_LOGIC;
           Dir :out STD_LOGIC;
           reg_counter : out STD_LOGIC_VECTOR (31 downto 0):= (others => '0'));
end encoder_control;

architecture Behavioral of encoder_control is
type state_type is (ST0,ST1,ST2,ST3,ST4);
signal PS,NS: state_type;
signal counter: integer:= 0;
begin

comb_proc: process(PS,A,B,Sys_clk,Reset)
begin
if (Reset = '1') then
PS <= ST0;
counter <= 0;
Error <= '0';
Dir <= '0';  --check if reset active
elsif(rising_edge(Sys_clk))then --if no reset then PS is NS on clock pulse
    PS <= NS; --else needed
case PS is  --state machine 
    when ST0 => 
        if(A = '0' and B = '0') Or (A2 = '1' and B2 = '1') then
            counter <= counter+1;
            Dir <= '1';
            NS <= ST1;
             elsif(A = '1' and B = '1') Or (A2 = '0' and B2 = '0') then
                counter <= counter -1;
                Dir <= '0';
                NS <= ST3;
             elsif(A = '1' and B = '0') Or (A2 = '0' and B2 = '1')then
                NS <= ST4;
             else NS <= ST0;
                counter <= counter;
        end if;
    when ST1 => 
        if(A = '1' and B = '0') Or (A2 = '0' and B2 = '1')then
            counter <= counter+1;
            Dir <= '1';
            NS <= ST2;
             elsif(A = '0' and B = '1') Or (A2 = '1' and B2 = '0')then
                counter <= counter -1;
                Dir <= '0';
                NS <= ST0;
                --revolution -1?
             elsif(A = '1' and B = '1') Or (A2 = '0' and B2 = '0')then
                NS <= ST4;
             else NS <= ST1;
                counter <= counter;
        end if;    
   when ST2 => 
        if(A = '1' and B = '1') Or (A2 = '0' and B2 = '0')then
            counter <= counter+1;
            Dir <= '1';
            NS <= ST3;
             elsif(A = '0' and B = '0') Or (A2 = '1' and B2 = '1')then
                counter <= counter -1;
                Dir <= '0';
                NS <= ST1;
             elsif(A = '0' and B = '1') Or (A2 = '1' and B2 = '0')then
                NS <= ST4;
             else NS <= ST2;
                counter <= counter;
        end if;
  when ST3 => 
        if(A = '0' and B = '1') Or (A2 = '1' and B2 = '0')then
            counter <= counter+1;
            Dir <= '1';
            NS <= ST0;
            --revolution +1
             elsif(A = '1' and B = '0') Or (A2 = '0' and B2 = '1')then
                counter <= counter -1;
                Dir <= '0';
                NS <= ST2;
             elsif(A = '1' and B = '1') Or (A2 = '0' and B2 = '0')then
                NS <= ST4;
             else NS <= ST3;
                counter <= counter;
        end if;
   when ST4 => 
        counter <= 0;
        Error <= '1';
   when others => 
   counter <= 0;
   NS <= ST0;
end case;
end if;
--reg_counter <= std_logic_vector(to_signed(counter, reg_counter'length)); --convert integer to vector
end process comb_proc;

reg_counter <= std_logic_vector(to_signed(counter, reg_counter'length)); --convert integer to vector
 end Behavioral;

试验台：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

entity Encoder_test1 is
end Encoder_test1;

architecture Behavioral of Encoder_test1 is
signal A : STD_LOGIC;
signal A2 : STD_LOGIC;
signal B : STD_LOGIC;
signal B2 : STD_LOGIC;
signal I : STD_LOGIC;
signal I2 : STD_LOGIC;
signal Reset : STD_LOGIC;
signal Error : STD_LOGIC := '0';
signal Dir : STD_LOGIC := '0';
signal Sys_clk : STD_LOGIC;
signal reg_counter : STD_LOGIC_VECTOR(31 downto 0):= (others => '0');
COMPONENT encoder_control
Port(
A : IN STD_LOGIC;
A2 : IN STD_LOGIC;
B : IN STD_LOGIC;
B2 : IN STD_LOGIC;
I : IN STD_LOGIC;
I2 : IN STD_LOGIC;
Reset : IN STD_LOGIC;
Error : OUT STD_LOGIC;
Dir : OUT STD_LOGIC;
Sys_clk : IN STD_LOGIC;
reg_counter : OUT STD_LOGIC_VECTOR(31 downto 0));
END component;
begin
i1: encoder_control
PORT MAP(
A => A,
A2 => A2,
B => B,
B2 => B2,
I => I,
I2 => I2,
Reset => Reset,
Error => Error,
Dir => Dir,
Sys_clk => Sys_clk,
reg_counter => reg_counter);

t_prcs_A: process
begin
loop
A <= '0';
wait for 25000 ps;
A <= '1';
wait for 50000ps;
A <= '0';
wait for 25000 ps;
end loop;
end process t_prcs_A;

t_prcs_A2: process
begin
loop
A2 <= '1';
wait for 25000 ps;
A2 <= '0';
wait for 50000ps;
A2 <= '1';
wait for 25000ps;
end loop;
end process t_prcs_A2;

t_prcs_B: process
begin
loop
B <= '0';
wait for 50000 ps;
B <= '1';
wait for 50000ps;
end loop;
end process t_prcs_B;

t_prcs_B2: process
begin
loop
B2 <= '1';
wait for 50000 ps;
B2 <= '0';
wait for 50000ps;
end loop;
end process t_prcs_B2;

t_prcs_I: process
begin
loop
I <= '0';
wait for 25000 ps;
end loop;
end process t_prcs_I;

t_prcs_I2: process
begin
loop
I2 <= '1';
wait for 25000 ps;
end loop;
end process t_prcs_I2;

t_prcs_Reset: process
begin
loop
--Reset <= '1';
--wait for 5000 ps;
Reset <= '0';
wait;
end loop;
end process t_prcs_Reset;

t_prcs_Sys_clk: process
begin
loop
Sys_clk <= '0';
wait for 5000 ps;
Sys_clk <= '1';
wait for 5000ps;
--if(now >= 1000000 ps) then wait; end if;
end loop;
end process t_prcs_Sys_clk;
end Behavioral;

仿真output：

Answer 1

reg_counter output 没有什么可以“修复”的。 模拟中显示的值 (0083f64c) 只是一个以十六进制记录的数字 (8648268)。 这与在二进制系统中写下一个数字基本相同（例如 5 是二进制中的“0101”），但这里以 16 为底而不是 2 为底。

https://en.wikipedia.org/wiki/Hexadecimal

如果您仍想显示十进制数，则模拟工具中可能有一些选项（不确定您使用的是哪一个）。