标签[cpu-architecture]

CPU或微控制器的硬件微体系结构(x86,x86_64,ARM等)。

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为什么你们永远不帮我过去这些东西?

Click on the link... httpsref.surveyj.cocman108点击链接... httpsref.surveyj.cocman108 The Zoom era begins, and for many people, sharing a single family co
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一旦识别出一个序列就会停止的状态机的真值表

There was a question i would like to ask here if possible.如果可能的话,我想在这里问一个问题。 I want to build the truth table of a State Machine that once recognizes a
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27

识别串行输入(-,-)的定序器的状态机(不在乎,不在乎)

Im new at this so i apologize in advance that if i make some mistakes while writing this question!我是新手,所以如果我在写这个问题时犯了一些错误,我提前道歉! THere was this questi
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44

浮点指令和浮点运算有什么区别?

I've been studying computer performance metrics and I have a doubt about MFLOPS.我一直在研究计算机性能指标,但我对 MFLOPS 有疑问。 By definition, MFLOPS is (NumberOfFloati
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29

为什么IRET指令会将EIP增加4?

From the Intel 80386 Programmer's Reference Manual:来自 Intel 80386 程序员参考手册:IRET is similar to RET except that IRET increments EIPby an extra four bytes
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10

哪些数据在执行前被加载而不是进入寄存器?

Before a certain operation is to be performed on the data by ALU, Will the operands have to be loaded into the register from memory to perform?在ALU对数据
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19

标签大小和缓存位练习

I am studying for my computer architecture exam that is due tomorrow and am stuck on a practice exercise regarding tag size and the total number of ca
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44

ADDM指令(Assembly-MIPSArchitectue)后的时钟周期如何简单解释?

lw ($t0), 8($s1) (load word) reads data from memory and writes it in a register. lw ($t0), 8($s1) (加载字)从内存中读取数据并将其写入寄存器。 A modified version of lw is a
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33

谁将进程的数据加载到数据路径中的寄存器组中?

When a process is in the running state and for example lets say we want to add two numbers therefore the instruction register will have the instructio
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73

C++在不同平台/架构上浮动和加倍

For context, I'm developing a library for Arduino to transfer data packets over LoRa receivers.对于上下文,我正在为 Arduino 开发一个库,以通过 LoRa 接收器传输数据包。 Question I'
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45

虚拟地址空间和虚拟内存有什么区别?

When a process is created by the user a virtual space address is created which is is the size 4g for a 32 bit os (0 to 2^32-1)?当用户创建一个进程时,会创建一个虚拟空间地址,
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在多周期MIPS上,所有I型指令是否占用相同数量的周期?

Do all I-type MIPS instructions take the same number of cycles in a multi-cycle datapath?在多周期数据路径中,所有 I 型 MIPS 指令是否采用相同数量的周期? I know R-type have the s
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18

valgrind的cachegrind仍然是2021年的首选工具吗?

I'm a long-time user of cachegrind for program profiling, and recently went back to check the official documentation once more: https://valgrind.org/d
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68

使用2的补码计算8位数字的加法

For the addition operations below, find the result that would be given by a computer using 8-bit, 2's complement numbers:对于下面的加法运算,找出计算机使用 8 位 2 的补码给出
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27

有没有衡量软CPU性能效率的指标?

I am trying to select a soft core CPU to implement on an FPGA .我正在尝试选择一个软核 CPU来在FPGA上实现。 There are many to choose from, with different levels of perfo
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如果我在冯诺依曼架构中有MDR,那么CIR的目的是什么?

From the fetch decode execute cycle of the Von Neumann Architecture, at a basic level, here is what I understand:从 Von Neumann Architecture 的 fetch de
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38

电路解码所需的最小输入位数

I'm learning about computer architecture and I was reading about encoders and decoders.我正在学习计算机体系结构,并且正在阅读有关编码器和解码器的信息。 In a MIPS processor, the opcod
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74

计算机体系结构中流水线中的“延迟加载”和“延迟分支”有什么区别?

This is from the book Computer System Architecture by M. Morris Mano.这是 M. Morris Mano 所著的 Computer System Architecture 一书。 About delayed load : "A pr
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47

如何解释程序集并将其编写为类似RISC的微操作

I am learning assembly and came across this practice.我正在学习汇编并遇到了这种做法。 the book i am using is : Randal E. Bryant, David R. O'Hallaron - Computer System
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为什么clflush是x86中的非特权指令?

While investigating on cache attacks against x86 Intel processors, I fail to understand why clflush is an unprivileged instruction.在调查针对 x86 Intel 处理器

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