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使用gcc以32位模式对64位值进行原子读/写

[英]Atomic reads/writes of 64 bit values in 32 bit mode with gcc

Is there any intrinsic or other way in gcc of persuading it to do 64 bit reads and writes atomically rather than as 2 32 bit writes? 在gcc中,是否有任何内在的或其他方式说服它执行原子的64位读取和写入,而不是2个32位写入? (At least in one or two places). (至少在一两个地方)。

Currently I'm having to do __sync_lock_test_and_set and __sync_fetch_and_add to get it to do the reads/writes atomically, but the CPUs in question have 64 bit fetch and store instructions. 目前,我必须执行__sync_lock_test_and_set__sync_fetch_and_add才能进行原子读取/写入,但是有问题的CPU具有64位读取和存储指令。

I'd prefer not to write loads of inline assembler (presumably one for each CPU we have to support) with #ifs spread around. 我不希望编写带有#if的内联汇编程序负载(大概每个要支持的CPU一个)。

I'm currently using gcc 4.4.6 and am unlikely to get that upgraded in the short term. 我目前使用的是gcc 4.4.6,短期内不太可能进行升级。

If you use "long long" the memory access won't be atomic. 如果使用“ long long”,则内存访问将不是原子的。

However maybe a "double" memory access may be atomic when using a 64-bit CPU (even in a 32 bit program): 但是,在使用64位CPU(甚至在32位程序中)时,“双”内存访问可能是原子的:

union {
    long long ll;
    double d;
} u;

u.ll = my_value;
*(double *)&my_long_long_variable = u.d;

However if the number "my_value" in this example will result in a "signalling NaN" value for ud then you may get an exception when doing this this way! 但是,如果此示例中的数字“ my_value”将导致ud的“ signaling NaN”值,则以这种方式进行操作时可能会出现异常!

Maybe the compiler will not even use FPU registers for this code. 也许编译器甚至不会为该代码使用FPU寄存器。 In this case the memory access won't be atomic and assembler programming will be needed. 在这种情况下,内存访问将不是原子的,并且需要汇编程序编程。 You'll definitely need to use either FPU registers or XMM/MMX/... registers for atomic 64-bit accesses. 您绝对需要使用FPU寄存器或XMM / MMX / ...寄存器来进行原子64位访问。

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