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计算缓存对处理器总体CPI的影响

[英]Calculating the effect of the cache on the overall CPI of the processor

How does one calculate the effect of L1 and L2 cache's on the overall CPI of the processor given base CPI, miss rate % of L1 and L2 caches and access times of L1, L2, and the memory 给定基本CPI,L1和L2高速缓存的未命中率百分比以及L1,L2和存储器的访问时间,如何计算L1和L2高速缓存对处理器总体CPI的影响

To find the CPI of L1 cache you would use: 要查找L1缓存的CPI,可以使用:

CPI = BaseCPI + (% of L1 Miss x Memory Access Time)

So I imagine that for L2 it would be something like: 因此,我认为对于L2来说,它将类似于:

CPI = BaseCPI + (% of L1 Miss x L2 Access Time) + ( % which I am confused about x Memory Access time)

How would one go about finding that second percentage? 如何找到第二个百分比?

I know that is has to do with the miss rate % of L2 but is it necessary to multiply by L1 Miss Rate % since L2 Miss will only happen after an L1 miss? 我知道这与L2的未命中率%有关,但是是否必须乘以L1的未命中率%,因为L2未命中只会在L1的未命中之后发生?

Yes, the miss rate of the L2 means the % of misses out of total L2 accesses. 是的,L2的未命中率表示未命中的次数占总L2访问次数的百分比。 Total L2 accesses are the total number of memory accesses * miss rate of the L1. L2总访问次数是内存访问总数* L1的未命中率。

So, your calculation should be - 因此,您的计算应为-

CPI = BaseCPI + (% of L1 Miss x L2 Access Time) + ( %L1 miss rate x % L2 miss rate x Memory Access time)  

or more conveniently: 或更方便的是:

CPI = BaseCPI + (% of L1 Miss x (L2 Access Time + (%L2 miss rate x Memory Access time)))

That's also not very accurate - you didn't specify the rate of memory operations, the above is assuming that every instruction is going to lookup the caches, which is a bit exaggerated. 这也不是很准确-您没有指定内存操作的速率,上面的假设是每条指令都将查找缓存,这有点夸张。 If you have a rate of loads/stores in the program you'll have to factor it in as well. 如果您在程序中有一定的加载/存储速率,则还必须考虑它。

By the way, in the real world you also need to add the following to the total L2 accesses: 顺便说一句,在现实世界中,您还需要将以下内容添加到总的L2访问中:

  1. L1 writebacks L1回写
  2. Code reads, if originating from a separate instruction L1 如果代码来自单独的指令L1,则会读取代码
  3. HW prefetching 硬件预取

But these are usually ignored in simple calculations as this (and you don't know the % of modified lines, so you can't deduce how many writebacks you'll have anyway). 但这通常在简单的计算中会被忽略(并且您不知道修改行的百分比,因此无论如何您都无法推断出有多少写回)。

One more note - it's not really The CPI of the cache , the cache itself doesn't perform instructions or cares about their timing. 还有一点需要注意-并不是The CPI of the cache ,缓存本身不执行指令或不在乎其时序。 The proper term would be - The effect of the cache (or any other feature) on the overall CPI of the processor . 合适的术语是- The effect of the cache (or any other feature) on the overall CPI of the processor

I think you are not taking into account the Average Number of Memory Accesses per Instruction (AMAPI). 我认为您没有考虑每条指令的平均内存访问数(AMAPI)。

For example, if there are 30% of load/store instructions, this number would be 1.3 (one access to fetch the instruction and 0.3 due to memory access instructions) 例如,如果有30%的加载/存储指令,则此数字将为1.3(一次访问可获取指令,而由于内存访问指令则为0.3)

So 所以

CPI = BaseCPI + (AMAT - ideal memory access time) x AMAPI

Being AMAT the Average Memory Access Time. 作为AMAT的平均内存访问时间。 For a two-level hierarcchy: 对于两个层次的层次结构:

AMAT = L1_hit_latency + L1_miss_rate x (L2_hit_latency + L2_miss_rate x Main_Memory_latency)

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