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获取/释放内存订购示例

[英]acquire/release memory ordering example

I don't understand this sample from here : 我从这里不了解此示例:

" Assuming 'x' and 'y' are initially 0: “假设'x'和'y'最初为0:

-Thread 1-
 y.store (20, memory_order_release);

 -Thread 2-
 x.store (10, memory_order_release);

 -Thread 3-
 assert (y.load (memory_order_acquire) == 20 && x.load (memory_order_acquire) == 0)

 -Thread 4-
 assert (y.load (memory_order_acquire) == 0 && x.load (memory_order_acquire) == 10)

Both of these asserts can pass since there is no ordering imposed between the stores in thread 1 and thread 2. 这两个断言都可以通过,因为线程1和线程2中的存储之间没有强加顺序。

If this example were written using the sequentially consistent model, then one of the stores must happen-before the other (although the order isn't determined until run-time), the values are synchronized between threads, and if one assert passes, the other assert must therefore fail. 如果此示例是使用顺序一致的模型编写的,那么其中一个存储必须发生-在另一个存储之前(尽管直到运行时才确定顺序),这些值在线程之间同步,并且如果一个断言通过,则因此,其他断言必须失败。 "

Why in acquire/release two assert can pass? 为什么在acquire/release两个断言可以通过?

When your memory model is not sequentially consistent, then different threads can see a different state of the world, and in such a way that there is no single, global state (or sequence of states) that is consistent with what both thread see. 当您的内存模型顺序不一致时,不同的线程可以看到不同的世界状态,并且没有与这两个线程看到的一致的单个全局状态(或状态序列)。

In the example, thread 3 could see the world as follows: 在示例中,线程3可以看到如下世界:

x = 0
y = 0
y = 20    // x still 0

And thread 4 could see the world as follows: 线程4可以看到如下世界:

x = 0
y = 0
x = 10    // y still 0

There is no global sequence of state changes of the world that is compatible with both those views at once, but that's exactly what's allowed if the memory model is not sequentially consistent. 世界上没有全局状态变化的序列可以立即与这两个视图兼容,但是如果内存模型不是顺序一致的,那正是允许的情况。

(In fact, the example doesn't contain anything that demonstrates the affirmative ordering guarantees provided by release/acquire. So there's a lot more to this than what is captured here, but it's a good, simple demonstration of the complexities of relaxed memory orders.) (实际上,该示例不包含任何说明释放/获取所提供的肯定性排序保证的内容。因此,这里所捕获的内容远不止于此,但它是轻松存储顺序的复杂性的很好的简单演示, 。)

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