[英]How to set all the bits to be 0 in a two-dimensional array in Verilog?
I've built a 8*2bits array to represent a piece of memory in Verilog 我已经构建了一个8 * 2bits阵列来表示Verilog中的一块内存
reg [1:0] m [0:7]
There is a reset signal for this memory and if reset is 1, all the bits in this memory should be reset to 0. But I don't know how to set all the bits of m in a concise way, because if there are hundreds thousands of bits in the memory, the following way is obviously unfeasible. 该存储器有一个复位信号,如果复位为1,则该存储器中的所有位应复位为0.但我不知道如何以简洁的方式设置m的所有位,因为如果有数百位在内存中数千位,以下方式显然是不可行的。
always@(posedge clk or posedge reset)
begin
if (reset)
begin
m[0]<=2'b00;
m[1]<=2'b00;
m[2]<=2'b00;
m[3]<=2'b00;
m[4]<=2'b00;
m[5]<=2'b00;
m[6]<=2'b00;
m[7]<=2'b00;
end
else
....
end
Use a for
loop: 使用
for
循环:
integer i;
always@(posedge clk or posedge reset)
begin
if (reset)
begin
for (i=0; i<8; i=i+1) m[i] <= 2'b00;
end
else
....
end
This is described in the IEEE Std 1800-2012 (Section 12.7.1 The for-loop, for example). 这在IEEE Std 1800-2012中描述(例如,第12.7.1节“for循环”)。
If you can use the current system verilog syntax, then this should work: 如果您可以使用当前系统verilog语法,那么这应该工作:
always_ff @(posedge clk or posedge reset)
begin
if(reset) begin
m <= '{default:2'b00};
end
else
...
end
See section 5.11 (Array Literals) of the 1800-2012 IEEE standard . 请参阅1800-2012 IEEE标准的 5.11节(阵列文字)。
This is actually the one place where for loops are meant to be used. 这实际上就是要使用for循环的地方。
for (i=0; i<8; i++)
begin
m[i] <= 2'b00;
end
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