默认的“ make”行为从何而来？

Question

I'm pretty new to Makefiles; thus, I encountered a question for which I can't come up with a good google search to help answer.

I am running a virtual OS which has a distro of fedora setup by someone else. If I construct my own Makefile in a directory, I can setup my .c files to compile however I like. Yet, if I simply run make test , whereby in my directory exists test.c , I will get the following : clang -ggdb3 -std=c99 -Wall -Werror test.c -lcs50 -lm -o test .

My question following this observation was where does this default, seemingly universal, make behavior come from? In other words, where does this Makefile, if it is one, sit on my file system?

Answer 1

make has several predefined implicit rules . Two of which are:

Compiling C programs no is made automatically from nc with a recipe of the form '$(CC) $(CPPFLAGS) $(CFLAGS) -c'.

Linking a single object file n is made automatically from no by running the linker (usually called ld) via the C compiler. The precise recipe used is '$(CC) $(LDFLAGS) no $(LOADLIBES) $(LDLIBS)'.

Note, make is smart enough to effectively concatenate the above two into one rule when it makes sense:

... could be done by using the '.o' object files as intermediates, but it is faster to do the compiling and linking in one step, so that's how it's done.

You can dump the predefined rules with make -pn . eg:

$ make -pn -f /dev/null | grep -A3 '^%: %.c$'
make: *** No targets.  Stop.
%: %.c
#  commands to execute (built-in):
    $(LINK.c) $^ $(LOADLIBES) $(LDLIBS) -o $@

$

Answer 2

This goes for GNU make, which normally is the default make implementation on linux.

There's no default Makefile on your file system containing the default rules. There are however implicit rules built into make that are in effect whether you supply a makefile or not, and what make does when invoked is documented here .

These rules knows eg how to build an executable from a .c source file. You can learn about those implicit rules here ,

eg make has this default rule when building an executable:

n is made automatically from no by running the linker (usually called ld) via the C compiler. The precise recipe used is '$(CC) $(LDFLAGS) no $(LOADLIBES) $(LDLIBS)'

Meaning if you run make test it will try to create an executable test from the file test.o, and you can set the respective CC/LDFLAGS/etc. variables that will be used when linking.

And as another implicit rule it can build a .o file from a .c file, so the above will look for test.o , and try to rebuild that using the rule:

no is made automatically from nc with a recipe of the form '$(CC) $(CPPFLAGS) $(CFLAGS) -c'.

Ie the implicit rules when running make test will first compile test.c and then link test.o using the compiler you specify with the CC envirnment variable(or the default compiler cc ) and the various compiler/linker flags if you set then as environment variables.

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