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是否可以对合金中的逻辑门建模

[英]is it possible to model a logic gate in alloy

I'm a new Alloy learner. 我是一名新的Alloy学习者。 I have a few things in mind I would like to know. 我想知道几件事。

Is it possible to create an element? 是否可以创建元素?

How would you model an AND logic gate? 您将如何对AND逻辑门建模?

My idea wich is useles is something like 我的想法是用油菜是这样的

open util/ordering[Time]
sig Time {frame: set gate}


abstract sig gate{}
sig ABinCout extends gate{ 
getA    : A,
getB    : B,
outputsC    : C,
} 


abstract sig Signals {}
sig A extends Signals{}
sig B extends Signals{}
sig C extends Signals{}


fact{first.frame = gate && no gate.getA && no gate.getB && no gate.outputsC } 

pred GateAB [t,t' : set Time,Gate : ABinCout]{
one a : A  | one b : B | {
Gate.getA = Gate.getA + a 
Gate.getB = Gate.getB + b
}}

pred GateABparaC [Gate : set ABinCout]{
one a : Gate.getA | one b : Gate.getB | one c : C{
    Gate.getA = Gate.getA - a
    Gate.getB = Gate.getB - b
    Gate.outputsC = Gate.outputsC + c

}}

pred GateC [Gate : set ABinCout]{
one c : Gate.outputsC | {
    Gate.outputsC =Gate.outputsC - c
}}

fact{
all t : Time, t' : t.next | one cel: ABinCout{
 GateAB[t,t',cel]
}}


run{ }for exactly 2 Time, 1 ABinCout, 3 A, 3 B, 1 C 

I can literally say i know nothing about alloy, but i would like to represent the gate alone... then I spawn 2 inputs... then in another frame it makes an output which is not any of the inputs! 我可以从字面上说我对合金一无所知,但我想单独代表门...然后生成2个输入...然后在另一个帧中它生成的输出不是任何输入!

Thanks in advance 提前致谢

If there is something I should read or now to do this task please say it. 如果有什么我应该阅读或现在要执行此任务的,请说出来。

It is not clear what exactly you're trying to achieve with your gates. 目前尚不清楚您到底想达到什么目的。 Hopefully my example below will clarify certain things about Alloy and help you design whatever gates you want. 希望我下面的示例将阐明有关Alloy的某些内容,并帮助您设计所需的任何浇口。

In this simple example, there is an abstract sig representing signals, and exactly two different concrete kinds of signals: One and Zero . 在这个简单的示例中,有一个抽象信号代表信号,正好是两种不同的具体信号: OneZero Next, an abstract gate is modelled to have a set of signals on its input (the ins field) and exactly one signal on its output ( out field). 接着,一个抽象的栅极被建模为具有一组在其输入端的信号(在ins在其输出(场)和正好一个信号out场)。 Finally, I defined 3 concrete sigs modelling the standard AND, OR, and NOT gates; 最后,我定义了3个对标准AND,OR和NOT门建模的具体信号。 for each of those sigs I added an appended fact to establish the relationship that must hold between the signals found on the input and the output (eg, the output of an AND gate is One if and only if all of its inputs are One s). 为每个SIGS的我增加了一个附加的事实来建立那些必须在输入和输出中发现的信号之间保持的关系(例如,一个输出AND门是One当且仅当所有的其输入是One或多个) 。

Then I thought it would be useful to show how you can model more complex gates composed of several simple ones. 然后,我认为展示如何建模由几个简单的门组成的更复杂的门将很有用。 I defined the xorgate predicate which asserts that the given input signals ( a , b ) and gates ( and1 , and2 , not1 , not2 , or1 ) are together forming a XOR gate ("connected" as in the picture below) 我所定义的xorgate谓词,它断言给定的输入信号( ab )和栅极( and1and2not1not2or1 )一起形成一个异或门(“连接”如在下面的图片)

AND,NOT和OR门的XOR门

Now, the best part about Alloy is that you can have a run command that will simulate this XOR gate by finding instances satisfying this predicate. 现在,有关Alloy的最好的部分是您可以拥有一个run命令,该命令将通过查找满足该谓词的实例来模拟此XOR门。 You can also also have a check command that checks that for all possible inputs on this XOR gate, its output is One if and only if the inputs are different (which is how the XOR gate should work). 您还可以有一个check命令,该命令检查并且仅当输入不同时(对于XOR门而言应如此),对于此XOR门上的所有可能输入,其输出均为One Executing this check in Alloy finds no counterexample. 在Alloy中执行此检查不会找到反例。

abstract sig Signal {}
one sig One extends Signal {}
one sig Zero extends Signal {}

abstract sig Gate {
  ins: set Signal,
  out: one Signal
} 

sig AND extends Gate {}{ out = One iff ins in One }
sig OR  extends Gate {}{ out = Zero iff ins in Zero }
sig NOT extends Gate {}{ #ins = 1 and out = Signal - ins }

pred xorgate[a, b: Signal, and1, and2: AND, not1, not2: NOT, o1: OR] {
  not1.ins = a
  and1.ins = b + not1.out
  not2.ins = b
  and2.ins = a + not2.out
  or1.ins = and1.out + and2.out
}

run xorgate for 5

check {
  all in1, in2: Signal |
    all a1, a2: AND, n1, n2: NOT, o1: OR {
      xorgate[in1, in2, a1, a2, n1, n2, o1] implies (o1.out = One iff in1 != in2)
    }
} for 5

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