如何根据Makefile中各自的标头依赖关系来构建多个源文件？

Question

I found it obscure to use make utility to generate header dependencies makefile for the source file and using this build the library or create executable accordingly.

1)

As suggested in the manual:

http://www.gnu.org/software/make/manual/html_node/Automatic-Prerequisites.html#Automatic-Prerequisites

I tried with the approach mentioned over there (In my case dependency files are present under obj/):

obj/%.d:%.cpp
    @set -e; rm -f $@; \
    g++ -MM $(CPPFLAGS) ${INC_FLAGS} $< > $@.$$$$; \
    sed 's,\($*\)\.o[ :]*,\1.o $@ : ,g' < $@.$$$$ > $@; \
    rm -f $@.$$$$

But this throws a shell error:

/bin/sh: cannot create obj/xyz.d.23030: Directory nonexistent

However obj directory is present, I didn't understand the use of sed command. The manual explains that it replaces any " .obj : .cpp " rule to ". obj .dep : .cpp ", But How ?

2) I also tried the approach mentioned over here :
http://mad-scientist.net/make/autodep.html

obj/%.o : %.c
    g++ -MMD ${CPPFLAGS} ${INC_FLAGS} -c $$<  -o $$@
    @cp obj/$*.d obj/$*.P; \
    sed -e 's/#.*//' -e 's/^[^:]*: *//' -e 's/ *\\$$//' \
        -e '/^$$/ d' -e 's/$$/ :/' < $*.d >> $*.P; \
    rm -f $*.d

Using this dependency file is generated but following error message is asserted:

"/bin/sh: cannot open obj/%.P: No such file"
sed: -e expression #2, char 4: unterminated `s' command

Again use of sed is not clear.

This becomes more obfuscate ... Here In the second approach if I don't add separate rule to create dependency files and generate them at the time of object creation, As "g++ -MP -MMD -c" creates both .o and .d. But how .o will be compiled again using the dependency makefile which is generated in the same command ?

I appreciate any help in resolving the errors occurred, And helping me in understanding this. Or Please suggest some elegant approach to do the same.

EDIT : (As suggested in the comment) In the second approach using both -MMD and -MP it works as expected, But I can't understand how it's working. Here sed comamnd is not required, and source gets rebuild if related header is modified:

obj/%.o : %.c g++ -MMD -MP ${CPPFLAGS} ${INC_FLAGS} -c $$< -o $$@

But As described in gcc manual page , If I didn't interpreted it wrong -MMD used to generate the dependency(excluding system header) file and -MP used to generate empty rule for each header, But it only modifies the object rule: ie,

obj/%.o obj/%.d : %.cpp (This is what sed is doing as mentioned in GNU make manual)

or something like,

obj/%.o : %.cpp (list of dependent headers for particular .cpp file)

What is the use of following two commands and how it works ?

a) sed 's,\\($*\\)\\.o[ :]*,\\1.o $@ : ,g' < $@.$$$$ > $@;

b)

sed -e 's/#.*//' -e 's/^[^:]*: *//' -e 's/ *\\$$//' \
                -e '/^$$/ d' -e 's/$$/ :/' < $*.d >> $*.P;

Answer 1

However obj directory is present,

Apparently it isn't. That's the first thing you need to solve.

I didn't understand the use of sed command. The manual explains that it replaces any ".obj : .cpp" rule to ".obj .dep : .cpp" , But How ?

The special make variable $* contains the stem that matched the pattern of the target, which will be the part of the target that matches the pattern %

The sed command replaces obj/%.o: with obj.o obj.d: , exactly as the Make manual says. To explain "how" you need to understand sed, but it's not a very complicated sed command.

Using this dependency file is generated but following error message is asserted:

That make recipe has a # character, which means everything after it is a comment, you need to escape it with \\#

However, if you're using GCC it's easier to just add -MMD to the normal recipe for generating object files, which will produce the .d files as a side-effect of compilation, so you don't need a separate target for the .d files.

Answer 2

So this is a makefile I wrote for one of my modules at university, you can try using it, when you call make it generates all the files and links all the files without needing to define anything extra in the file. There is a lot of excess stuff here, but I did this quite a while ago, but you can take things out and play around with it to see what you can remove. Hope this helps =)

CC=g++

WARNING_FLAGS=-Wall -Wextra -Weffc++ -Winit-self -Wmissing-include-dirs \
-Wswitch-default -Wswitch-enum -Wunused-parameter -Wstrict-overflow=5 \
-Wfloat-equal -Wshadow -Wc++0x-compat -Wconversion -Wsign-conversion \
-Wmissing-declarations -Wstrict-null-sentinel -Woverloaded-virtual -Wsign-promo\
-Werror -pedantic
FORMATTING_FLAGS=-fno-pretty-templates -fmessage-length=80 -fdiagnostics-show-option
CFLAGS=${WARNING_FLAGS} ${FORMATTING_FLAGS} -g -std=c++0x -pipe  -frepo

LDFLAGS=
LDLIBS=-lGL -lGLEW -lglut -lGLU -lX11 -lXi -lm -lpng

TARGET=main
OBJECTS=$(addsuffix .o, $(basename $(shell ls *.C | grep -v Test)))
HEADERS=$(addsuffix .h, $(basename $(shell ls *.h | grep -v Test)))

TEST_LDFLAGS=-lboost_unit_test_framework
TEST_LDLIBS=${LDLIBS}
TEST_TARGET=test
TEST_OBJECTS=$(addsuffix .o, $(basename $(shell ls *.C | grep -v main)))

CLEAN_TARGETS=$(addsuffix .o, $(basename $(shell ls *.C))) ${TARGET} ${TEST_TARGET} *.rpo *.gch makefile.dep

all: ${OBJECTS} 
    ${CC} ${LDFLAGS} ${LDLIBS} $^ -o ${TARGET}

test: ${TEST_OBJECTS}
    ${CC} ${TEST_LDFLAGS} ${TEST_LDLIBS} $^ -o ${TEST_TARGET}

%.o:
    ${CC} ${CFLAGS} -c ${LDFLAGS} $< -o $@

Test.o: Test.C Makefile
    ${CC} -c $< -o $@

clean:
    rm ${CLEAN_TARGETS}

makefile.dep: *.[Ch]
    for i in *.C; do gcc -std=c++0x -MM "$${i}"; done > $@
include makefile.dep