在C ++中使用-o和-c的Makefile语法

Question

It's been a while since I've done a makefile. I have inherited some code that is built with the following line in a makefile

$(CC) $(FLAGS) -c -o $*.o $*.cpp

Why would you use -c and -o in the same line. Doesn't the -c make it so that you build the objects without linking?

EDIT Here is the complete makefile, now I get an error saying cpp.cpp No such file or directory

.SUFFIXES: .o .cpp

CC=g++

MAIN_OBJS = \
    main.o \
    f1.o \
    f2.o \

all:
    $(CC) -c -o $*.o $*.cpp
    $(CC) $(MAIN_OBJS) -o final

Shouldn't the $*.cpp find all the .cpp files in my current path (and they are there)

Answer 1

As you say, -c means make object files without linking.

-o means you want to override the default output file name and specify your own. So -o $.o means the output file name would be the same as the input file name but with .o on the end.

You might do this if you were planning to have this Makefile rule usable with a number of different compilers, some of which might have a different default output file name for object files.

The man page for gcc describes -o like this:

-o file

Place output in file file. This applies regardless to whatever sort of output is being produced , whether it be an executable file, an object file, an assembler file or preprocessed C code. If -o is not specified, the default is to put an executable file in a.out, the object file for source.suffix in source.o, its assembler file in source.s, a precompiled header file in source.suffix.gch, and all preprocessed C source on standard output.

Answer 2

Yes, what you said makes sense.
As we know, -c will compile the source files and produce the assembly files.
After that, we normally use -o to link all those assembly files and produce a executable file.
What follows -o is the name of the output executable file.

And if the -c and -o are used in the same line, it means the output assembly file produced by -c is named what follows -o .