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产生PWM与GPIO速度有何关系?

[英]How is generating PWM related to GPIO speed?

During GPIO configuration and initialization we, for example, may set the pin speed to 50MHz, 100 MHz, but we also may set it to 2MHz. 例如,在GPIO配置和初始化期间,我们可以将引脚速度设置为50MHz,100 MHz,但也可以将其设置为2MHz。 As far as I know less speed = less power consumption. 据我所知,更少的速度=更少的功耗。 How is generating PWM related to pin speed? 产生PWM与引脚速度有何关系? When I want to generate 300Hz or 1kHz PWMs, can I set pin speed to 2MHz? 当我想产生300Hz或1kHz PWM时,可以将引脚速度设置为2MHz吗?

Thanks in advance for answers. 预先感谢您的回答。

The speed ratings you are talking about - 50 MHz, 100 MHz, 2 MHz - are basically slew rates controlling how fast the I/O pin changes state. 您正在谈论的速度额定值-50 MHz,100 MHz,2 MHz-基本上是压摆率,用于控制I / O引脚改变状态的速度。

This has essentially nothing to do with the programming of the counters/timers used to actually generate the signal - it should not be confused with a clock prescaler which reduces the clock rate going into the timer, potentially drastically reducing the power consumption (most power in CMOS circuits is used charging and discharging implicit capacitance when changing state) but also the timing resolution. 这实际上与用于实际生成信号的计数器/计时器的编程无关,不应与clock prescaler混淆,后者会降低进入计时器的时钟速率,从而可能大大降低功耗( CMOS电路用于在状态改变时对隐式电容进行充电和放电,同时也用于定时分辨率。

In contrast, the slew rate reduction is something like a crude low-pass filter on the output. 相反,压摆率的降低类似于输出上的粗略低通滤波器。 It does potentially mean less power consumed driving the output (or at least the power spread over a greater amount of time), but most of the power consumed by a counter/timer will be in clocking the counter itself. 这的确可能意味着驱动输出所需的功耗更少(或至少在较长时间内分散了功耗),但是计数器/计时器所消耗的大部分功率将用于为计数器本身计时。

If your output frequency is well below the slew rate limit, and your external circuit can tolerate slow transitions you could try setting this. 如果您的输出频率远低于压摆率限制,并且您的外部电路可以承受缓慢的过渡,则可以尝试设置该值。

Of course if your output frequency approaches the slew rate limit, you may find that your signal fails to drive all the way to valid logic levels. 当然,如果您的输出频率接近转换速率极限,则可能会发现信号无法一直驱动到有效逻辑电平。

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