GNU Make：使用两个C / C ++目标和不同命令的更好方法

Question

Q: Here is my Makefile fragment below:

SRCS+=$(wildcard *.c *.cpp)
OBJECTS=$(addprefix $(OBJ_DIR)/, $(patsubst %.c,%.o,$(SRCS:.cpp=.o)))
# .....
$(OBJ_DIR)/%.o: %.cpp
    $(CXX) -ggdb -Wall -Wextra -Werror $(INC) $(C_FLAGS) -c -o $@ $<

$(OBJ_DIR)/%.o: %.c
    $(CC) -ggdb -Wall -Wextra -Werror $(INC) $(C_FLAGS) -c -o $@ $<

How can I refactor expression after "OBJECTS" and remove duplication of the similar rules for .cpp and .%c?

Answer 1

OBJECTS := $(patsubst %,$(OBJ_DIR)/%.o,$(basename $(SRCS)))
# Note that you may not need this variable at all.

COMPILE_ARGS = -ggdb -Wall -Wextra -Werror $(INC) $(C_FLAGS) -c -o $@ $<

$(OBJ_DIR)/%.o: %.cpp
    $(CXX) $(COMPILE_ARGS)

$(OBJ_DIR)/%.o: %.c
    $(CC) $(COMPILE_ARGS)