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使用UVM ML和Specman和SV跟踪TLM端口连接

[英]trace TLM port connections using UVM ML wiith Specman and SV

原文 2015-04-27 08:51:35 2 2 specman

I am using UVM-ML on Incisive, and cannot figure out why data is not passing between my SV collector and e scoreboard. 我在Incisive上使用UVM-ML，无法弄清楚为什么数据没有在SV收集器和电子记分板之间传递。 How can I see which TLM ports are connected, and in general debug ML environments? 在一般的ML调试环境中，如何查看已连接的TLM端口？

2 个解决方案

Uvm_ml_phase-运行连接Uvm_ml_print_tree Uvm_ml_print_connections

You can use uvm_ml_phase -run connect. 您可以使用uvm_ml_phase -run connect。 after this phase the ports are connected and you can view the uvm_ml tree and all the ports relations via design browser. 在此阶段之后，端口已连接，您可以通过设计浏览器查看uvm_ml树和所有端口关系。

Specman e UVM：为什么要继承uvm_ *单位？ - Specman e UVM: Why to inherit from uvm_* units?

Specman中的端口绑定调试 - port binding debugging in specman

Specman UVM记分牌基本问题 - Specman UVM Scoreboard basic questions

Specman UVM：直接访问寄存器和使用read_reg_val（）有什么区别？ - Specman UVM: What is the difference between access a register directly and using read_reg_val()?

Specman UVM：当值写入另一个寄存器时，如何更新寄存器的值？ - Specman UVM: How update a value of a register when the value was written to another register?

Specman UVM：write_reg { .field == 2;} 和有什么区别；和 write_reg_fields？ - Specman UVM: What is the difference between write_reg { .field == 2;}; and write_reg_fields?

Specman覆盖范围：是否有一种使用变量定义范围的方法？ - Specman coverage: Is there a way to define ranges using variable?

Specman在科莫多 - specman on Komodo

什么是使用SPECMAN的IDE - what is the IDE for using SPECMAN

Specman e：有没有办法将simple_port的hdl_path连接到否定的Verilog端口？ - Specman e: Is there a way to connect a simple_port's hdl_path to negated verilog port?

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相关问题 Specman e UVM：为什么要继承uvm_ *单位？ - Specman e UVM: Why to inherit from uvm_* units? Specman中的端口绑定调试 - port binding debugging in specman Specman UVM记分牌基本问题 - Specman UVM Scoreboard basic questions Specman UVM：直接访问寄存器和使用read_reg_val（）有什么区别？ - Specman UVM: What is the difference between access a register directly and using read_reg_val()? Specman UVM：当值写入另一个寄存器时，如何更新寄存器的值？ - Specman UVM: How update a value of a register when the value was written to another register? Specman UVM：write_reg { .field == 2;} 和有什么区别；和 write_reg_fields？ - Specman UVM: What is the difference between write_reg { .field == 2;}; and write_reg_fields? Specman覆盖范围：是否有一种使用变量定义范围的方法？ - Specman coverage: Is there a way to define ranges using variable? Specman在科莫多 - specman on Komodo 什么是使用SPECMAN的IDE - what is the IDE for using SPECMAN Specman e：有没有办法将simple_port的hdl_path连接到否定的Verilog端口？ - Specman e: Is there a way to connect a simple_port's hdl_path to negated verilog port?

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