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修改UVM序列项变量

[英]Modifying UVM sequence item variable

I am writing a new sequence item that is extending from an existing sequence item. 我正在写一个从现有序列项目扩展的新序列项目。 In the new sequence, I would like to extend the size of a variable in the existing sequence item, like so: 在新序列中,我想扩展现有序列项中变量的大小,如下所示:

Existing: 现有:

rand bit [9:0] var_mem;

New: 新:

rand bit [15:0] var_mem;

Whenever I run the sequence using the new extended sequence item, the transaction shows the size of var_mem as 10, not the expected 16. Is it possible to modify the size of a variable in the new extended sequence item, either in the sequence item or the corresponding sequence? 每当我使用新的扩展序列项运行序列时,事务都会将var_mem的大小显示为10,而不是预期的16。是否可以在新的扩展序列项中修改变量的大小?相应的顺序?

It is usually a bad idea to override variables in an extended class unless all methods that access the base variable are overridden as well. 除非扩展了所有访问基变量的方法,否则在扩展类中覆盖变量通常是一个坏主意。 The UVM does not support this very well, especially if you are using the field automation macros. UVM对此的支持不是很好,尤其是在使用现场自动化宏的情况下。

Your options are to declare the variable with the maximum size in the base class, and use another variable to represent the actual size. 您的选择是在基类中声明最大大小的变量,并使用另一个变量表示实际大小。 That size variable can be used to constrain the value during randomization, as well as pack/unpack methods you provide. 该大小变量可用于限制随机化过程中的值,以及您提供的打包/解包方法。

Another option is to use a parameterized class that defined the variable width. 另一种选择是使用定义变量宽度的参数化类。

Try using the parameter instead of bits width. 尝试使用参数代替位宽。 Here's the snippet of the code for your reference 这是代码段供您参考

class existing_seq extends uvm_sequences(response_item);
  rand bit [9:0] var_mem ;
endclass
class new_seq #(int size = 16) extends existing_seq;
  rand bit [size-1:0] var_mem ;
  existing_seq seq1;  
endclass

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