这个makefile有什么作用？

Question

I have the following makefile (Makefile.certify) and when I execute:

make -f Makefile.certify

It gives me a:

/bin/sh: line 23: -o: command not found

PROG=certify
TMP=/var/tmp
ARCH=x86_64
_CC=/bin/cc

all: ${PROG}

${PROG}: ${ARCH}
    @for mode in $? ; do \
            case $${mode} in        \
                    i386)           \
                            CC="${_CC} -g -D__x86";         \
                            ;;      \
                    i386-f64)       \
                            CC="${_CC} -D_FILE_OFFSET_BITS=64 -g -D__x86";\
                            ;;      \
                    amd64)          \
                            CC="${_CC} -m64 -g -D__x86 -D__ia64 -D__GNUC";\
                            ;;      \
                    *)              \
                            ;;      \
            esac;           \
            $${CC} -o ${TMP}/$${mode}/$@ ${TMP}/$@.c;       \
    done

I don't really use makefiles or c , but I have to deal with this one.

My questions are:

1. Why does for loop need a @ prefix?
2. What is the $? in the for loop?
3. What would be a possible execution of this makefile? Obviously it tries to compile my certify. c file based on the architecture of the system executing or something like this, but I fail to see how it will choose either i386 or amd64 etc.

I am using an x86 system running RHEL .

Answer 1

1. @ prefix is used for suppressing command print by make . If it is not present, make will print command before execution to output.

   You can remove it and see the difference.

2. $? is the dependency list. In your particular case ARCH is defined as a single entry "x86_64". So $? will be expanded into that value. But you can try to modify ARCH value in the following way:

    ARCH=x86_64 i386 

3. It tries to build certify binary for a given architecture from cerfify.c source file. Each binary will be located in own sub-directory:

    /var/tmp/{i386|x86_64|i386_f64}/certify 

Answer 2

1. @ is used to suppress the normal 'echo' of the command that is executed. Using it in the for loop is also new to me (does removing it change anything in the output?)

2. $? is one of the makefile automatic variables , this one means "The names of all the prerequisites that are newer than the target, with spaces between them"

3. It will iterate through $? , read above

Edit:

Example of $?

targetfile : firstfile secondfile thirdfile
    cat $? > $@

if targetfile is older than all the other 3 files , the makefile will concatenate the contents of firstfile , secondfile and thirdfile together in targetfile .