为什么内存屏障不只阻止每个特定内存地址的指令？

Question

As I understand it, a memory barrier will "separate" loads/stores (depending on what type of barrier is used) regardless of the memory address associated with the "fenced" instruction. So if we had an atomic increment, surrounded by loads and stores:

LOAD A
STORE B
LOAD C
LOCK ADD D    ; Assume full fence here
LOAD E
STORE F

the instructions operating on A, B and C would have to complete before D; and E and F may not start until after D.

However, as the LOCK is only applied to address D, why restrict the other instructions? Is it too complicated to implement in circuitry? Or is there another reason?

Answer 1

The basic reason is because the basic intent of a fence is to enforce ordering, so if the fence affected only reads/writes of the specific item to which it was applied, it wouldn't do its job.

For example, you fairly frequently have patterns like:

prepare some data
signal that the data is ready

and:

consume some data
signal that the memory used for the data is now free

In such cases, the memory location used as the "signal" is what you're probably going to protect with the fence--but it's not the only thing that really needs to be protected.

In the first case, I have to assure that all the code that writes the data gets executed, and only after it's all done, the signal will be set.

Another thread can then see that the signal is set. Based on that, it knows that it can read all the data associated with the signal, not just the signal itself. If the fence affected only the signal itself, it would mean that the other code that was writing the data might still execute after the signal--and then we'd get a collision between that code writing the data, and the other code trying to read the data.

In theory, we could get around that by using a fence around each individual piece of data being written. In reality, we almost certainly want to avoid that--a fence is fairly expensive, so we'd usually prefer to write a significant amount of data, then use a single fence to indicate that the entire "chunk" of memory is ready.