如何在makefile中为目标编写特定规则？

Question

I know the title is quite ambiguous but I just don't know how to describe my problem concisely. Please edit that if you want.

Currently my makefile is like the following:

CC = g++
CFLAGS = -Wall -g

TARGET = foobar
SRC_FILES = foo.cpp bar.cpp main.cpp
OBJ_FILES := $(SRC_FILES:.cpp=.o)

$(TARGET): $(OBJ_FILES)
    $(CC) $(CFLAGS) $^ -o $@

%.o: %.cpp %.h
    $(CC) $(CFLAGS) -c $<

clean:
    rm -rf *.o $(TARGET)

The problem is that this structure requires main.cpp to have a main.h header file, which I don't really have. How can I handle this nicely?

Answer 1

GCC (and probably Clang) can build a list of dependencies for you; This way, you can simply make your object files from their source (cpp) file:

depend: .depend

.depend: $(SRC_FILES)
        rm -f ./.depend
        $(CC) $(CFLAGS) -MM $^ -MF  ./.depend;

include .depend

%.o: %.cpp
    $(CC) $(CFLAGS) -c $<

You might also find interest in the makedepend tool.