petalinux问题在zynq上重置为逻辑

Question

I've been developing a system on a Zynq chip using Petalinux. One thing that has remained a mystery to me is a means to issue a reset to the logic side of the chip from petalinux. In Vivado, when a memory mapped peripheral is added, a processor reset module is automatically inserted, and the reset is connected to the FCLK_ARESETx_N pin. Is there a way to drive this reset from user-space? I can happily control a logic reset from a memory mapped module but I've been curious about this.

Answer 1

There used to be a sysfs interface in slcr.c for exactly this purpose but it was removed in this commit . The reason for removal was because "reset controls for peripherals should never be used, since device drivers control the peripherals"...

At the time you could assert the FCLK_ARESETx_N signal by writing 1 to /sys/class/xslcr_reset/fpgax_out/reset .

If you still want to use the reset signals from userspace, you can talk to the SLCR registers manually using the devmem command (or mmap , etc.). For me, the appropriate register is at 0xf8000240. This comes from...

• SLCR base address from the .dts is 0xf8000000
• offset for FPGA resets from slcr.c is 0x240

the nth bit will control the nth reset signal. To reset on all lines from userspace, use:

devmem 0xf8000240 32 0xf #Raise reset
devmem 0xf8000240 32 0x0 #Lower reset

Hope this helps!