x86 / 64与ARM缓存未命中/分支错误预测损失

Question

Is there any significant or fundamental difference between the penalty of cache misses and branch mispredictions for ARM and x86/64 processors?

I understand that mileage may vary depending on concrete model and whole configuration of a machine. But still wondering if there's anything.

Answer 1

Fundamentally a ~32MHz 3-stage Cortex-M0 pipeline works the same way as a ~3GHz 40-stage NetBurst P4 pipeline - if the next instruction/data isn't available yet, you're just going to have to wait until it is.

Actual cycle counts, timing, and everything else will depend on many different microarchitecture/system/implementation details and vary hugely even within a single architecture (compare said NetBurst P4 to a 486DX-40, or said Cortex-M0 to an X-Gene 2, for example).