如何在chisel中编写异步复位

Question

How to add the reset signal to the sensitivity list in the generated Verilog code when writing a Chisel code, for example the code below for D flip flop:

val x = Reg(init = UInt(0, width = 1))
    x := io.D
    io.Q := x 

will generate a Verilog code as this:

always @(posedge clk) begin
    if(reset) begin
      x <= 1'h0;
    end else begin
      x <= io_D;
    end
end

as seen the reset is synchronous with the clock, how to code Chisel to generate something like this:

always @(posedge clk or posedge reset) begin
    if(reset) begin
      x <= 1'h0;
    end else begin
      x <= io_D;
    end
end

where the reset signal is in the sensitivity list and hence asynchronous.

Edit: As pointed by chrisvp there is another question here and a discussion in chisel-users google group here

Answer 1

Since Chisel 3.2.0, asynchronous reset is supported. The example code can be implemented with the following:

import chisel3._
import chisel3.stage.ChiselStage

class Foo extends RawModule {
  val clk   = IO(Input(Clock()))
  val reset = IO(Input(AsyncReset()))
  val io    = IO(Input(new Bundle{ val D = UInt(1.W) }))
  val out   = IO(Output(Bool()))

  val x = withClockAndReset(clk, reset) { RegNext(io.D, init=0.U) }
  out := x
}

This will then produce the following Verilog logic for register x :

always @(posedge clk or posedge reset) begin
  if (reset) begin
    x <= 1'h0;
  end else begin
    x <= io_D;
  end
end

To use synchronous reset, change the type of reset from AsyncReset to Bool .

Answer 2

This question is a copy of How to generate an asynchronous reset verilog always blocks with chisel

If really required, you could consider forcing this by considering the rst as a second clock domain as described in the Chisel manual , though I wouldn't recommend to do so.