具有两个可执行文件的递归makefile

Question

I have a project which contains two main functions, one is for implementation of my program and the other main function is for testing the program. I searched the web for this but found almost nothing that was about recursive makefile with two executables.

Makefile

CC = clang
CFLAGS = -g -Wall

PROG = suggest

OBJDIR = objects
OBJS = $(OBJDIR)/suggest.o $(OBJDIR)/engine.o $(OBJDIR)/table.o $(OBJDIR)/levenshtein.o

# ... link them
$(PROG): $(OBJS) $(OBJDIR)
    $(CC) $(CFLAGS) $(OBJS) -o $(PROG)

$(OBJDIR)/table.o:
    $(MAKE) -C table.c
    cp ../file1/table.c/table.o $(OBJDIR)

$(OBJDIR)/levenshtein.o:
    $(MAKE) -C levenshtein.c
    cp levenshtein.c/levenshtein.o $(OBJDIR)

# build them all...
$(OBJDIR)/%.o: %.c $(OBJDIR)
    $(CC) $(CFLAGS) -c -o $@ $<

$(OBJDIR):
    mkdir -p $(OBJDIR)

clean:
    rm -rf $(OBJDIR) $(PROG)

In the above file, engine.c is a main function that does the implementation of my program however i have another main function as well, called test.c that does testing on my file. What i want is, when i run the make command, it should only build the engine.c main function (by default) but if i want to test my program i should be able to run the test.c main function by specifying something like this, for instance make test .

---

The problem is i don't have a makefile for test file. My directory is like this: engine.c , suggest.c , test.c and then i have another folder called levenshtein.c and that has got its own makefile. Also i just want to work with only two makefiles. I have already written one which is in the levenshtein.c folder and the one that i have problem is this one as this folder contains two main functions.I would want a conditional compilation based on the command.

Answer 1

Try this; Adding the new target TEST and conditionally linking in either engine.o or test.o. This will only work if your test program doesn't require any of the functions or data in engine.o If it does you may want to conditionally compile the two main functions using something like -DTEST_PROGRAM

Since you're using other functions and data from engine.o you should add something like #if USE_TEST_PROGRAM #endif around the main(...) function inside of engine.c and define the USE_TEST_PROGRAM flag in your makefile as shown below. This will have the side effect of compiling engine.c twice (once into your OBJDIR for your program suggest and once in your top dir for your test program).

CC = clang
CFLAGS = -g -Wall

PROG = suggest
TEST = test

OBJDIR = objects
OBJS = $(OBJDIR)/suggest.o $(OBJDIR)/table.o $(OBJDIR)/levenshtein.o

# ... link them
$(PROG): $(OBJS) $(OBJDIR)
    $(CC) $(CFLAGS) $(OBJS) $(OBJDIR)/engine.o -o $(PROG)

$(TEST): $(OBJS) $(OBJDIR)
    $(CC) $(CFLAGS) -DUSE_TEST_PROGRAM=1 engine.c $(OBJS) $(OBJDIR)/test.o -o $(PROG)

$(OBJDIR)/table.o:
    $(MAKE) -C table.c
    cp ../file1/table.c/table.o $(OBJDIR)

$(OBJDIR)/levenshtein.o:
    $(MAKE) -C levenshtein.c
    cp levenshtein.c/levenshtein.o $(OBJDIR)

# build them all...
$(OBJDIR)/%.o: %.c $(OBJDIR)
    $(CC) $(CFLAGS) -c -o $@ $<

$(OBJDIR):
    mkdir -p $(OBJDIR)

clean:
    rm -rf $(OBJDIR) $(PROG)

Answer 2

You don't want to use recursion for what you're doing.

By the sounds of your description you want to have a single makefile, which builds one of two final targets: either test or engine . For test , it should compile and link test.c . For engine , it should compile and link engine.c .

If this is correct, you could build a makefile with two targets as so:

test engine: $(PROG)

.PHONY: test engine

So each target depnds on $(PROG) . You then modify your makefile to have the correct list of objects to build:

OBJS := ....

ifneq ($(filter test,$(MAKECMDGOALS)),)
    #test was a command goal, add test.o to the targets:
    OBJS+=$(OBJDIR)/test.o
else ifneq ($(filter engine,$(MAKECMDGOALS)),)
    #engine was a command goal, add test.o to the targets:
    OBJS+=$(OBJDIR)/engine.o
else
    #neither were command goals.  set default:
    OBJS+=$(OBJDIR)/engine.o
fi

$(PROG): $(OBJS)
     @$(CC) $(CFLAGS) $? -o $@

now when you run make test , it will add test.o to $(OBJS) , build and link ( $? will contain all .o files), otherwise it will add engine.o to $(OBJS) . Make will compile all the $(OBJS) and build your target.

One other thing. You have:

$(OBJDIR):
    mkdir -p $(OBJDIR)

(which is good, but not so good, you have:

$(PROG): $(OBJS) $(OBJDIR)

First of all, it will try to build the objects before it creates the object directory (which can cause a build failure). Also, if objdir is made ahead of time, and the compilation works, the timestamp on $(OBJDIR) is updated each time a file inside that directory changes... So it it would likely be newer than $(PROG) , causing it to be rebuilt often when it doesn't need to be. The correct way to do this is:

$(OBJS): | $(OBJDIR)

notice the | , which means order-only dependency, meaning it won't rebuild $(OBJS) if $(OBJDIR) has a newer timestamp, but it will build the directory before any of the objects.

Answer 3

All of the above answers were very helpful but i still wasn't able to run my program. After getting some hints from the above answers, i was able to come up with a simplified version of makefile. The above ones are also accurate depending on the setup of your directories. This is how i did it.

(NOTE: this may not be the best solution)

TEST = test.c engine.c levenshtein.c/levenshtein.c ../subdir1/table.c
PROG = suggest.c engine.c levenshtein.c/levenshtein.c ../subdir1/table.c
OBJ_TEST = $(TEST:.c=.o)
OBJ_PROG = $(PROG:.c=.o)

CC = clang
CFLAGS = -g -Wall

test: $(OBJ_TEST)
    $(CC) $(OBJ_TEST) -o $@

suggest: $(OBJ_PROG)
    $(CC) $(OBJ_PROG) -o $@

.SUFFIXES: .c .o
.c.o:
    $(CC) $< $(CFLAGS) -c -o $@

clean:
    rm -rf *.o

I had a parent directory which contained two more folders. My directory set-up looked like this:

Project/

|_____ subdirectory that contained table.c

|_____ another subdirectory that contained my engine.c, suggest.c and test.c, and it contained levenshtein.c as well which was a separate folder.

So for any future readers if you are reading this, take note of your directories and then try to create a makefile as it will make life less stressful.