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伊卡洛斯不知道如何解析localparam数组?

[英]Icarus doesnt know how to parse localparam arrays?

I am using v10 of Icarus Verilog, Windows 8.1 and am having troubles compiling 1D arrays like: 我正在使用Icarus Verilog,Windows 8.1的v10,并且在编译1D数组时遇到麻烦,例如:

localparam [15:0] A[0:5]  = {
    0,
    10920, 
    21840,
    32760,
    43680,
    54600
};

or 2D array like: 或2D数组,例如:

localparam [1:0] B[0:5][0:2] = {
    {2'b00, 2'b10, 2'b01},
    {2'b10, 2'b00, 2'b01},
    {2'b10, 2'b01, 2'b00},
    {2'b00, 2'b01, 2'b10},
    {2'b01, 2'b00, 2'b10},
    {2'b01, 2'b10, 2'b00}
};

When I try to compile this using iverilog inside command prompt like: iverilog -o tb.vvp ".v files here" I get the following errors: 当我尝试在命令提示符下使用iverilog编译此iverilog -o tb.vvp ".v files here"iverilog -o tb.vvp ".v files here" ,出现以下错误:

tb.v:39: syntax error
tb.v:39: error: syntax error localparam list.
tb.v:54: syntax error
tb.v:54: error: syntax error localparam list.

Lines 39 and 54 are lines where upper two arrays are located. 第39和54行是上面两个数组所在的行。

What is wrong and how can I fix this ridicilous error? 有什么问题,如何解决这个荒谬的错误?

Verilog does not support unpacked arrayed parameters/localparams; Verilog不支持解压缩数组参数/ localparams; SystemVerilog does. SystemVerilog可以。 See: 看到:

Icarus Verilog (iverilog) has limited SystemVerilog support. Icarus Verilog(iverilog)具有有限的SystemVerilog支持。 EDAplayground currently includes Icarus Verilog 0.10.0 11/23/14, which does not support unpacked arrayed parameters with SystemVerilog enabled. EDAplayground当前包含Icarus Verilog 0.10.0 11/23/14,它不支持启用SystemVerilog的解压缩数组参数。 You can try with the latest version of Icarus. 您可以尝试使用最新版本的Icarus。 Enable SystemVerilog by changing your file extinctions from .v to .sv , you may need to add the -g2012 compile option. 通过将文件灭绝从.v更改为.sv来启用SystemVerilog,您可能需要添加-g2012编译选项。

If that doesn't work, you will need to convert the array into a large vector. 如果这不起作用,则需要将数组转换为大向量。 You can slice the array with the +: operator (Added in Verilog 2001 and supported with Icarus Verilog. See Indexing vectors and arrays with +: ). 您可以使用+:运算符对数组进行切片(在Verilog 2001中添加,并受Icarus Verilog支持。请参见使用+:索引向量和数组 )。 Or change to another simulator that supports SystemVerilog. 或更改为另一个支持SystemVerilog的模拟器。

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