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当代处理器与纯冯·诺依曼架构有何不同?

[英]How do contemporary processors differ from a pure von Neumann architecture?

So I never really understood the von Neumann architecture, and have started to revise it as I wasn't in school during the lessons of the CPU. 因此,我从来没有真正了解过冯·诺依曼(von Neumann)的体系结构,并且因为在我上CPU课期间不在学校,所以开始对其进行修改。 Can't really get help through my teacher as they wont respond to their email. 由于我的老师不会回复电子邮件,因此无法真正获得帮助。

I have learnt about the von Neumann architecture, and now I need to know how the architecture differs from a contemporary processor. 我已经了解了冯·诺依曼架构,现在我需要知道该架构与现代处理器的不同之处。

I know that contemporary processors sometime use a mixture of Harvard and von Neumann architecture by using Harvard for the communication between the control unit and caches though for cost effective reasons von Neumann is used between the main memory and cpu. 我知道当代处理器有时通过使用哈佛在控制单元和缓存之间进行通信来混合使用哈佛和冯·诺依曼的体系结构,尽管出于成本效益的原因,冯·诺依曼被用于主存储器和CPU之间。

The specification point wants to know how it differs though, and I will be very thankful for any responses that might answer the question. 规范点想知道它有什么不同,对于可能回答该问题的任何答复,我将非常感谢。

Thanks! 谢谢!

Well I think I may have answered my own question, the specification just wanted to know how it differs from the pure von Neumann architecture. 好吧,我想我可能已经回答了我自己的问题,该规范只是想知道它与 von Neumann体系结构有何不同。 It differs as contemporary processors use a mixture of architectures from Harvard and von Neumann for many reasons (mainly cost) and where speed advantages outweigh the complexity costs. 它与众不同,因为现代处理器出于多种原因(主要是成本)使用哈佛和冯·诺依曼的混合架构,而速度优势胜于复杂性成本。

Contemporary processors use a mixture of both von Neumann and Harvard architecture, which differs from a pure von Neumann architecture by using von Neumann architecture for the main memory to the CPU and Harvard for the control unit and caches. 现代处理器使用冯·诺依曼架构和哈佛架构的混合,这与纯冯·诺依曼架构的区别在于,冯·诺依曼架构用于主存储器,CPU和哈佛用于控制单元和高速缓存。

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