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如何在ARM体系结构中读取协处理器

[英]How read coprocessor registers in ARM architecture

I'm trying to read CP15 coprocessor in the following System-on-chip 我正在尝试在以下片上系统中读取CP15协处理器

Cortex A7 - ARMv7-A Cortex A7 - ARMv7-A

Below my snippet 在我的片段下方

void main (void)
{
    unsigned int reg_value = 0;
    asm volatile("mrc p15, 0, %0, c0, c0, 0" : "=r"(reg_value) );
    printf("reg_value: %d", reg_value);
}

I don't know if this is the correct way to read the coprocessor register but its compilation is completed without errors. 我不知道这是否是读取协处理器寄存器的正确方法,但是它的编译完成没有错误。 The problem is arisen during its execution (the code is executed in root): 问题出现在执行期间(代码在root中执行):

Illegal instruction

If I use gdb I obtain the following result: 如果我使用gdb,我会得到以下结果:

   0x000086a0 <+16>:    str r3, [r11, #-40] ; 0x28
=> 0x000086a4 <+20>:    mrc 15, 0, r3, cr0, cr0, {0}
   0x000086a8 <+24>:    str r3, [r11, #-40] ; 0x28

Why I'm not able to read coprocessor registers? 为什么我无法读取协处理器寄存器? What's wrong with my code? 我的代码出了什么问题?

It seems that you are trying to access MIDR: Main ID Register (from the ARMARMv7 B4.1.105) using the instruction 您似乎正在尝试使用该指令访问MIDR:主ID寄存器(来自ARMARMv7 B4.1.105)

MRC p15, 0, <Rt>, c0, c0, 0    ; Read MIDR into Rt

However, as you are in Linux and executing an application, you are in usermode (PL0) and ARMARMv7 specifies in the usage constraints of MIDR that 但是,当您在Linux中并执行应用程序时,您处于用户模式(PL0)和ARMARMv7中,在MIDR的使用限制中指定

Only accessible from PL1 or higher. 仅可从PL1或更高版本访问。

So only accessible at PL1, PL2, PL3. 所以只能在PL1,PL2,PL3上访问。 To access it you need to create a driver running at PL1 which will do the read of MIDR. 要访问它,您需要创建一个运行在PL1的驱动程序,它将读取MIDR。 Then, in your application, open this driver to get the data using IOCTL for example. 然后,在您的应用程序中,打开此驱动程序以使用IOCTL获取数据。

You can also try to access the kernel mode (PL1) using a SVC call from PL0, but this would imply modifying your kernel SVC handler. 您也可以尝试使用来自PL0的SVC调用来访问内核模式(PL1),但这意味着修改内核SVC处理程序。

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