我们可以合成一个简单的通用内存吗？

Question

I'm trying to synthesis with simple generic memory model within design compiler.

but I do find that some error messages as the below,

and I used the simple generic memory model as the below

module RAM_generic
 (clk,
 enb,
 wr_din,
 wr_addr,
 wr_en,
 rd_addr,
 rd_dout);

 parameter AddrWidth = 1;
 parameter DataWidth = 1;

 input clk;
 input enb;
 input signed [DataWidth - 1:0] wr_din;
 input [AddrWidth - 1:0] wr_addr;
 input wr_en;
 input [AddrWidth - 1:0] rd_addr;
 output signed [DataWidth - 1:0] rd_dout;

 reg [DataWidth - 1:0] ram [2**AddrWidth - 1:0];
 reg [DataWidth - 1:0] data_int;


 always @(posedge clk)
 begin
 if (enb == 1'b1) begin
 if (wr_en == 1'b1) begin
 ram[wr_addr] <= wr_din;
 end
 data_int <= ram[rd_addr];
 end
 end

 assign rd_dout = data_int;
endmodule

I want to know Can't we synthesis a simple generic memory? If yes, What am I supposed to do to synthesis the generic memory synthesis error?

Answer 1

Yes you can.

In FPGA's a single or dual ported memory will be mapped on the internal memory structures. (At least if you use the right syntax! Look for the FPGA application notes how to do that)

In an ASIC it will be made from registers. I needed a small triple ported memory (Two read and a write port all simultaneous) a few years back and it came out fine. Most FIFO's have a memory in them and 90% of them are made from registers.

Your code is missing 'endmodule'. I don't spot any other obvious errors.

Some tips:

• Using ((1 << AddrWidth) -1) will also work in old fashion Verilog.
• I would not use a default width/depth of 1 for a memory. You get [0:0] constructs which work, but why should you if eg 8x8 is more likely to be used.
• A generic memory should not be signed. By convention a generic memory is unsigned.
• Parameters are by convention all uppercase. (At least in every firm I worked it was)