一个周期以verilog排序

Question

i was trying to sort 9 random numbers in verilog. I use bubble sort(nested for loops) algorithm but i have a challenge. I want to sort them in one clk cycle but it does not do what i want. It needs at least 9 cycle to sort them.

always @(posedge clk)
begin

if(m >= 68 && sort_valid == 0) begin
    pool_sort[0] <= pool_buffer[66];
    pool_sort[1] <= pool_buffer[65];
    pool_sort[2] <= pool_buffer[64];
    pool_sort[3] <= pool_buffer[34];
    pool_sort[4] <= pool_buffer[33];
    pool_sort[5] <= pool_buffer[32];
    pool_sort[6] <= pool_buffer[2];
    pool_sort[7] <= pool_buffer[1];
    pool_sort[8] <= pool_buffer[0];

sort_valid <= 1;

 end

if(sort_valid == 1) begin
        for(k=0;k<8;k=k+1) begin
            if(pool_sort[k] < pool_sort[k+1]) begin
                pool_sort[k] <= pool_sort[k+1];
                pool_sort[k+1] <= pool_sort[k];
            end
        end
    if(sort_counter == 0) begin
        sort_valid <= 0;
        pool_out <= pool_sort[0];
    end
end
end

always @(posedge clk)
begin

if(sort_valid == 1) begin
sort_counter <= sort_counter - 1;
end
if(sort_counter == 0) begin
    sort_counter <= 8;
end

end
endmodule

This is my sorting algorithm so far.

Answer 1

Think upfront if you will need to sort many rounds of 9 numbers.

You can do sorting within 1 cycle, but the top frequency could be significantly limited. But then, it doesn't really matter if you spent 1 clock cycle at low frequency, or 9 clocks at much higher frequency.

If you will have many rounds, then you can pipeline sorting stages, getting new result on every clock cycle, with a few clock latency for a first result.

See also https://en.wikipedia.org/wiki/Bitonic_sorter , as more suitable for parallel sorting in hw with small number of inputs.

Answer 2

Here's a paramaterizable 1-clock cycle sorter for Verilog (inspired from here but I parameterized the module, reduced the number of cycles, and did some cleanup).

It'll do what you want in simulation but it'll probably be pretty big and ugly when you synthesize it.

module sort #(
    parameter NUM_VALS = 5,
    parameter SIZE     = 16
)(  input  wire clk,
    input  wire [NUM_VALS*SIZE-1:0] in,
    output reg  [NUM_VALS*SIZE-1:0] out
);
    reg [NUM_VALS*SIZE-1:0] sorted_bus;
    always @(posedge clk) begin
        out <= sorted_bus;
    end

    integer i, j;
    reg [SIZE-1:0] temp;
    reg [SIZE-1:0] array [1:NUM_VALS];
    always @* begin
        for (i = 0; i < NUM_VALS; i = i + 1) begin
            array[i+1] = in[i*SIZE +: SIZE];
        end

        for (i = NUM_VALS; i > 0; i = i - 1) begin
            for (j = 1 ; j < i; j = j + 1) begin
                if (array[j] < array[j + 1]) begin
                    temp         = array[j];
                    array[j]     = array[j + 1];
                    array[j + 1] = temp;
                end 
            end
        end

       for (i = 0; i < NUM_VALS; i = i + 1) begin
            sorted_bus[i*SIZE +: SIZE] = array[i+1];
       end
    end
endmodule

And a testbench:

module sort_tb;
    reg clk;
    reg  [16-1:0] in1,  in2,  in3,  in4,  in5;
    wire [16-1:0] out1, out2, out3, out4, out5;

    sort #(.NUM_VALS(5), .SIZE(16)) dut (
        .clk(clk),
        .in ({in1,  in2,  in3,  in4,  in5}),
        .out({out1, out2, out3, out4, out5})
    );

    always @(posedge clk) begin
        in1 <= $random;
        in2 <= $random;
        in3 <= $random;
        in4 <= $random;
        in5 <= $random;
    end

    always @(posedge clk) begin
        $display("In:  %0d %0d %0d %0d %0d", in1,  in2,  in3,  in4,  in5);
        $display("Out: %0d %0d %0d %0d %0d", out1, out2, out3, out4, out5);
    end

    initial begin
        #100;
        $finish;
    end

    always begin
        clk = 1'b0; #5;
        clk = 1'b1; #5;
    end
endmodule