RISC-V 分支偏移机器指令编码

Question

What's the decoded RISC-V assembly instruction of: 0001100 01010 11100 100 10001 1100011 ? From the specification i know, that the opcode is the BLT instruction and rs1 = x28, rs2 = x10.

But what is the encoded offset? imm[12|10:5] is 0001100 = 12 and imm[4:1|11] is 10001 = -8, right? Where will the jump go?

Answer 1

The RISC-V Instruction Set Manual lists the complete instruction set in chapter 19. The opcode (the 7 least significant bits) tells us that we deal with a B-type instruction. The funct3 bits ( [14:12] ) specify the BLT instruction.

The BLT instruction is encoded as follows:

This gives us:

	imm[12|10:5]	rs2	rs1	funct3	imm[4:1|11]	opcode
instruction	0001100	01010	11100	100	10001	1100011
value	0xc	0xa (x10)	0x1c (x28)	0x4	0x11	0x63

The immediate value is the concatenation of the instruction bits [31|7|30:25|11:8] : 0|1|001100|1000 = 0x4c8 . Note that the immediate value misses the bit at index 0 .

The RISC-V Instruction Set Manual states in 2.3 Immediate Encoding Variants :

There are a further two variants of the instruction formats (B/J) based on the handling of immediates, as shown in Figure 2.3. The only difference between the S and B formats is that the 12-bit immediate field is used to encode branch offsets in multiples of 2 in the B format. Instead of shifting all bits in the instruction-encoded immediate left by one in hardware as is conventionally done, the middle bits (imm[10:1]) and sign bit stay in fixed positions, while the lowest bit in S format (inst[7]) encodes a high-order bit in B format.

This is because RISC-V has a 16-bit instruction alignment constraint ( 1.2 Instruction Length Encoding ):

The base RISC-V ISA has fixed-length 32-bit instructions that must be naturally aligned on 32-bit boundaries. However, the standard RISC-V encoding scheme is designed to support ISA extensions with variable-length instructions, where each instruction can be any number of 16-bit instruction parcels in length and parcels are naturally aligned on 16-bit boundaries. The standard compressed ISA extension described in Chapter 12 reduces code size by providing compressed 16-bit instructions and relaxes the alignment constraints to allow all instructions (16 bit and 32 bit) to be aligned on any 16-bit boundary to improve code density.

Ergo we need to add a trailing 0 to the offset, which gives us: 0|1|001100|1000|0 = 0x990 .

The decoded instruction is: blt x28, x10, 0x990

Answer 2

.word 0x18ae48e3

blt x28,x19,hello
blt x28,x19,hello
blt x28,x19,hello
blt x28,x19,hello
blt x28,x19,hello
blt x28,x19,hello
blt x28,x19,hello
blt x28,x19,hello
blt x28,x19,hello
blt x28,x19,hello
blt x28,x19,hello
blt x28,x19,hello
blt x28,x19,hello
hello:
blt x28,x19,hello
blt x28,x19,hello
blt x28,x19,hello



00000000 <hello-0x38>:
   0:   18ae48e3            blt x28,x10,990 <hello+0x958>
   4:   033e4a63            blt x28,x19,38 <hello>
   8:   033e4863            blt x28,x19,38 <hello>
   c:   033e4663            blt x28,x19,38 <hello>
  10:   033e4463            blt x28,x19,38 <hello>
  14:   033e4263            blt x28,x19,38 <hello>
  18:   033e4063            blt x28,x19,38 <hello>
  1c:   013e4e63            blt x28,x19,38 <hello>
  20:   013e4c63            blt x28,x19,38 <hello>
  24:   013e4a63            blt x28,x19,38 <hello>
  28:   013e4863            blt x28,x19,38 <hello>
  2c:   013e4663            blt x28,x19,38 <hello>
  30:   013e4463            blt x28,x19,38 <hello>
  34:   013e4263            blt x28,x19,38 <hello>

00000038 <hello>:
  38:   013e4063            blt x28,x19,38 <hello>
  3c:   ff3e4ee3            blt x28,x19,38 <hello>
  40:   ff3e4ce3            blt x28,x19,38 <hello>

00000001001111100100001001100011
00000001001111100100000001100011
11111111001111100100111011100011


0 000000 1001111100100 0010 0 1100011
0 000000 1001111100100 0000 0 1100011
1 111111 1001111100100 1110 1 1100011 

you do see how to extract these numbers from the instruction as documented yes?

0 0 000000 0010 0
0 0 000000 0000 0
1 1 111111 1110 0

0 0000 0000 0100 = 0x0004 
0 0000 0000 0000 = 0x0000 (<-- hello label here)
1 1111 1111 1100 = 0x1FFC

Okay so no magic here, sometimes there is an offset, often there is an offset. Often the address of the next instruction is where the immediate is applied. With ARM for example the address of two instructions ahead is where the offset is applied.

from your instruction
0001100 01010 11100 100 10001 1100011
0 001100 01010 11100 100 1000 1 1100011
010011001000 (add implied zero for bit 0)
0 1001 1001 0000 = 0x990