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gem5中用于armv8处理器的未定义TLBI指令

[英]Undefined TLBI instruction for armv8 processor in gem5

I encountered a gem5 error while running gem5 fs simulation for aarch64 in bare metal mode. 在裸机模式下为aarch64运行gem5 fs仿真时遇到了gem5错误。 Especially, when my custom boot code tried to invalidate TLB with an assembly instruction tlbi ALLE3 , the simulator reported the following message: 特别是,当我的自定义启动代码尝试使用汇编指令tlbi ALLE3使TLB无效时,模拟器报告了以下消息:

system.cpu T0 : @core0+72    :   msr   tlbi_alle3, xzr    : IntAlu :
Undefined Instruction: Invoking Fault (AArch64 target EL) : Undefined Instruction cpsr:0x3c5 PC:0x2186c elr:0x2186c newVec: 0xa00

Also, I tested with "tlbi ALLE1" but it ended up with the same error. 另外,我使用“ tlbi ALLE1”进行了测试,但最终出现了相同的错误。 For your reference, I configured a cpu type with TimingSimpleCPU. 供您参考,我使用TimingSimpleCPU配置了CPU类型。 Based on the message, the passed tlbi instruction seems to be unimplemented in ARM64 processor model. 根据该消息,传递的tlbi指令似乎在ARM64处理器模型中未实现。 However, since I know that gem5 successfully boots Linux for aarch64 in fs mode, I am wondering how the case could handle the tlbi instruction. 但是,由于我知道gem5在fs模式下成功为aarch64引导了Linux,所以我想知道这种情况如何处理tlbi指令。 In other words, if the tlbi instruction is really unimplemented instruction in gem5, I think that booting Linux should also have run into the same error. 换句话说,如果tlbi指令实际上是gem5中未实现的指令,我认为引导Linux也应该遇到相同的错误。 Can I know if anyone has experienced the undefined instruction fault of tlbi in gem5? 我能知道是否有人在gem5中遇到过tlbi的未定义指令错误吗? Thanks for your answer/comment in advance. 感谢您的预先答复/评论。

Update1 : Further investigation showed that tlbi VMALLE3 did not cause any error, while tlbi ALLE3 instruction caused an undefined instruction fault. Update1 :进一步调查显示, tlbi VMALLE3不会引起任何错误,而tlbi ALLE3指令则导致未定义的指令错误。

The Linux kernel only exercises a subset of all ARM functionality. Linux内核仅行使所有ARM功能的子集。

For example, Linux v4.18 ARMv7 broke because it started using CSDB, and so we just marked that instruction as ignored for now: https://github.com/gem5/gem5/commit/33b311d8d8b8d527d500d62a35b50be63e41b556 which just emits a warning instead, since that instruction is implementation defined and could be a NOP. 例如,Linux v4.18 ARMv7之所以中断,是因为它开始使用CSDB,因此我们现在将该指令标记为已忽略: https : //github.com/gem5/gem5/commit/33b311d8d8b8d527d500d62a35b50be63e41b556只是发出警告,因为该指令是实现定义的,可以是NOP。

Notably, there are several ARMv8.x instructions which are not yet implemented. 值得注意的是,有几条尚未实现的ARMv8.x指令。

So I recommend the following: 因此,我建议以下内容:

  • grep the .isa files under src/arch/arm/isa/ and search for the exact tlbi encoding that you are using. grep src/arch/arm/isa/下的.isa文件,并搜索您正在使用的确切tlbi编码。

    Those files are responsible for the instruction decoding, so if an instruction is implemented, that is where you have to look. 这些文件负责指令的解码,因此,如果实现了指令,则必须在其中查找。

    There are already hits under tlbi , but make sure that your exact instruction bytes are going to the right place. tlbi下已经有命中,但是请确保您的确切指令字节在正确的位置。

    GDB step debug gem5 if necessary, and remember that there might be a decoding bug and that the bytes actually should be another instruction. GDB如有必要,请调试debug gem5,并记住可能存在解码错误,并且字节实际上应该是另一条指令。

  • Actually do a Linux kernel boot trace with --debug-flags=Exec and see if it contains the mentioned instruction. 实际上使用--debug-flags=Exec进行Linux内核启动跟踪,并查看它是否包含上述指令。

  • Provide a line of assembly that reproduces the problem, and a GNU GAS version used to assemble it so that others can reproduce. 提供可以重现该问题的汇编行,以及用于汇编该问题的GNU GAS版本,以便其他人可以重现该问题。

If you find that there is a missing encoding, and are able to implement it fully, or if it is a implementation defined NOP like CSDB just ignore it with a warning, send a patch on Gerrit and CC me. 如果您发现缺少编码,并且能够完全实现它,或者如果它是一个实现定义的NOP(如CSDB),则只需发出警告就忽略它,请在Gerrit和CC me上发送补丁。

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