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SystemVerilog Coverage:为枚举的每个元素创建一个bin

[英]SystemVerilog Coverage: Create a bin for each element of an enum

Say I have a enum which contains a list of valid commands or opcodes. 假设我有一个包含有效命令或操作码列表的枚举。 Is there a way to create a bin for each element of the enum? 有没有办法为枚举的每个元素创建一个bin?

class command_coverage;
  enum {SEQ_WRITE_16_BIT = 32'hBEEFFOOD, SEQ_READ_16_BIT = 32'hFACEFACE, 
        ... } my_valid_commands

  covergroup cg();
    command_cp : coverpoint cmd {
                   bins valid_commands[] = each element of enum;
                 }
  endgroup

  ...

endclass

I tried something like: 我尝试过类似的东西:

bins valid_commands[] = my_valid_commands;

or 要么

bins valid_commands[] = {[0:$] inside my_valid_commands};

But it didn't work as I wanted. 但它并没有按照我的意愿行事。

It can be done: 可以办到:

command_cp : coverpoint my_valid_commands {
    bins valid_commands[] = {[my_valid_commands.first:my_valid_commands.last]};

first and last are methods of the enum, which return the first and last values respectively. firstlast是枚举的方法 ,它们分别返回第一个和最后一个值。 These are then used as part of a range. 然后将它们用作范围的一部分。

Here's the display from Mentor Questa (other simulators are available - I have Questa installed on my PC): 这是Mentor Questa的显示屏(其他模拟器可用 - 我的PC上安装了Questa):

在此输入图像描述

Here's an MCVE : 这是一个MCVE

https://www.edaplayground.com/x/5rUu https://www.edaplayground.com/x/5rUu

module enum_cg;

  enum {SEQ_WRITE_16_BIT, SEQ_READ_16_BIT} my_valid_commands;

  covergroup cg();
    command_cp : coverpoint my_valid_commands {
      bins valid_commands[] = {[my_valid_commands.first:my_valid_commands.last]};
                 }
  endgroup

  cg cg0 = new;

  initial begin
    my_valid_commands = SEQ_WRITE_16_BIT;
    cg0.sample;
  end    

endmodule

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