如何将C编译输出文件（Linux内核模块）放在与源文件不同的目录中（使用Makefile）

Question

I have looked at these and at these other solutions but cannot write the correct Makefile to produce my wanted result.

So, I have this simple.c file. It simulates linux kernel module loading and removing. Location: /path/to/dir/simple.c

#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>

/* This function is called when the module is loaded. */
int simple_init(void)
{
       printk(KERN_INFO "Loading Module\n");

       return 0;
}

/* This function is called when the module is removed. */
void simple_exit(void) {
    printk(KERN_INFO "Removing Module\n");
}

/* Macros for registering module entry and exit points. */
module_init( simple_init );
module_exit( simple_exit );

MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Simple Module");
MODULE_AUTHOR("SGG");

I also have this Makefile in the same directory as simple.c , location: /path/to/dir/Makefile .

obj-m += simple.o
all:
        make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
clean:
        make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean

When on a terminal I run:

cd path/to/dir/
make

everything is compiled correctly (in the same directory path/to/dir/ .

What I want is this:

Location of simple.c in /path/to/dir/src/ .

Location of Makefile in /path/to/dir/ .

Location of the outputs in /path/to/dir/bin/ or/and /path/to/dir/obj/ .

When make is run, the outputs should end in the bin , obj directories.

There are some complications in the Makefile ( /lib/modules/$(shell uname -r)/build ) which I don't quite understand. All the various changes to the Makefile in order to reach the desired result, ended without success in errors.

How do I do it?

Edit:

The Makefile in /lib/modules/$(shell uname -r)/build has the following code:

VERSION = 4
PATCHLEVEL = 4
SUBLEVEL = 162
EXTRAVERSION =
NAME = Blurry Fish Butt

# *DOCUMENTATION*
# To see a list of typical targets execute "make help"
# More info can be located in ./README
# Comments in this file are targeted only to the developer, do not
# expect to learn how to build the kernel reading this file.

# o Do not use make's built-in rules and variables
#   (this increases performance and avoids hard-to-debug behaviour);
# o Look for make include files relative to root of kernel src
MAKEFLAGS += -rR --include-dir=$(CURDIR)

# Avoid funny character set dependencies
unexport LC_ALL
LC_COLLATE=C
LC_NUMERIC=C
export LC_COLLATE LC_NUMERIC

# Avoid interference with shell env settings
unexport GREP_OPTIONS

# We are using a recursive build, so we need to do a little thinking
# to get the ordering right.
#
# Most importantly: sub-Makefiles should only ever modify files in
# their own directory. If in some directory we have a dependency on
# a file in another dir (which doesn't happen often, but it's often
# unavoidable when linking the built-in.o targets which finally
# turn into vmlinux), we will call a sub make in that other dir, and
# after that we are sure that everything which is in that other dir
# is now up to date.
#
# The only cases where we need to modify files which have global
# effects are thus separated out and done before the recursive
# descending is started. They are now explicitly listed as the
# prepare rule.

# Beautify output
# ---------------------------------------------------------------------------
#
# Normally, we echo the whole command before executing it. By making
"/lib/modules/4.4.0-141-generic/build/Makefile" [readonly] 1650L, 57062C

Answer 1

I don't know if i have understood the question. First of all I recommend you to locate the source code in the SRC folder. After that, choose the dir where you want to create the Makefile.

The next step is to define the set of codes that you are going to need to link your program. Do not forget the path to the SRC folder.

Now it's time to create the object files. In this step, choose the option -o [path_obj]/[file_name].o.

The last step consist in to link the program, do not forget that the objects are in the [path_obj] folder.

A simple example could be:

#path definitions

SRC_path = /path_to_src/
OBJ_path = /path_to_obj/
BIN_path = /path_to_bin/

#lists definitions
SRC = [file1].c [file2].c
OBJ = $(addsuffix .o, $(basename ${SRC}))

#Suffixes definitions
.suffixes:
.suffixes: .c .o

#Create objects
.c.o:   gcc -I[include_files] -c $(SRC_path)$< -o $(OBJ_path)$@

#Link program
TAG:    gcc  $(addprefix $(OBJ_path), $(OBJ)) -o $(BIN_path)[program_name]

I hope you find it useful