如何避免必须手动从我的Makefile中的不同路径列出每个C文件？

Question

Currently I am having to list every single C-File in my makefile, which does not seem efficient. The C-Files exist in multiple folders and subfolders.

For example:

C_SOURCES =  \
Core/main.c \
Core/adc.c \
Core/buttons.c \
Core/config.c \
Core/delay.c \
Core/dsp/filter.c \
Core/ui/ui_definition.c \
... and so on
Core/system_stm32f4xx.c \
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c \
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c \

I also wonder how to make it work so that the Linker is taking the correct object-files. At the moment all object-files are getting saved into the 'build'-directory, as shown below:

all: $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).hex $(BUILD_DIR)/$(TARGET).bin

# list of objects
OBJECTS = $(addprefix $(BUILD_DIR)/,$(notdir $(C_SOURCES:.c=.o)))
vpath %.c $(sort $(dir $(C_SOURCES)))

# list of ASM program objects
OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASM_SOURCES:.s=.o)))
vpath %.s $(sort $(dir $(ASM_SOURCES)))

$(BUILD_DIR)/%.o: %.c Makefile | $(BUILD_DIR) 
    $(CC) -c $(CFLAGS) -Wa,-a,-ad,-alms=$(BUILD_DIR)/$(notdir $(<:.c=.lst)) $< -o $@

$(BUILD_DIR)/%.o: %.s Makefile | $(BUILD_DIR)
    $(AS) -c $(CFLAGS) $< -o $@

$(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) Makefile
    $(CC) $(OBJECTS) $(LDFLAGS) -o $@
    $(SZ) $@

$(BUILD_DIR)/%.hex: $(BUILD_DIR)/%.elf | $(BUILD_DIR)
    $(HEX) $< $@

$(BUILD_DIR)/%.bin: $(BUILD_DIR)/%.elf | $(BUILD_DIR)
    $(BIN) $< $@

I am also confused about how to change the .o-rule in the Makefile, in the case that the C-Files from the subfolders are also saved in the subfolders in the build directory. (If the 'Core/dsp/filter.c' gets saved under 'build/dsp/filter.o' or 'build/filter.o', how do I need to change the rule accordingly?)

Answer 1

You've asked a lot of different questions here, without a lot of specificity, so I'll just answer your first, clear question:

If you want make to find all the source files on its own rather than you listing them you can use the shell function to run find :

C_SOURCES := $(shell find Core Drivers -name \*.c -print)

You need to use := here to ensure that the find command is not re-run every time the $(C_SOURCES) variable reference is expanded, but is instead only run one time.

Answer 2

This works for me, regarding the including all .c files from sub-folders and linking object files issues.

#include .c files
SOURCES = $(shell echo ./**/*.c)

#obj file
OBJ = $(SOURCES:.c=.o)

Though I'm not sure if ./**/*.c works on Windows..