火箭芯片上的设置关联 TLB

Question

I am trying to address if Rocket Chip Generator supports a set-associative TLB (both for L1 and L2 TLB) but I cannot find any straightforward code about that in RocketCore.scala or PTW.scala . On the other hand changing the associativity of the Caches in HellaCache.scala is pretty straight-forward.

From my understanding L1 TLB is fully-associative and L2 TLB is direct-mapped.

Is there a straightforward way to change the set-associativity of the TLB on Rocket Chip that I am missing? If not, are there any resources that you could provide in order to help me add these features in Rocket Chip?

Thank you.

Answer 1

I implemented the configurable L1/L2 TLB on Rocket Chip myself, my code is upstream and merged in the official Rocket Chip repository .

In order to change the associativity and size of the L1 TLB you can tweak nTLBSets, nTLBWays in /src/main/scala/rocket/HellaCache.scala (only power of 2 sets/ways are allowed for now).

For the L2 TLB, you can tweak nL2TLBSets, nL2TLBWays in /src/main/scala/rocket/RocketCore.scala .

Answer 2

I finally implemented an L1 TLB Generator on Rocket Chip myself, it is still a work in progress as some stuff like replacement policies and TLB flushing are not fully implemented, but it works!

It required many modifications and a bit of reverse-engineering (documentation and comments are sparse) that would take ages to explain in detail, so you can check it out here .