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Question

I want to create separate executables for each directory named "test" in my project. Test directory has structure like this: test.mk

test (dir)
|__test.mk
|__testRun.c
|__testRun.h

test.mk contains dependencies for specific test, testRun.c is the test itself.

So hierarchy looks like this:

ROOT
|__Makefile
|__Module1 (dir)
  |__some files
  |__test (dir)
|__Module2 (dir)
   |__some files
   |__test (dir)
|__Module3 (dir)
   |__some files
   |__test (dir)
|__outdir  (dir)
   |__test1 (exec)
   |__test2 (exec)
   |__test3 (exec)

I want to run single Makefile in root parent directory. I want it to search for all test directories and create test executables in outdirectory . So far I have this:

Makefile

CFLAGS =    -I$(DIRTEST) -I$(DIRTEST)/..
OUTDIR=     ./outdirectory
DIRTEST =   $(shell find -type d -not -path "$(OUTDIR)/*" -name "test" -prune )

I have no idea how to create rule that creates target executable from sources and headers from separate directories. I was looking for solution for similar problem, but no luck so far.

Note: I do not want to use recursive make. test.mk looks for example like this:

SRCTEST = module1/test/testRun.c \
          module1/module1.c
CFLAGS += -Imodule1

Answer 1

You can use bash scripts files for building variables, in case if you are avoiding a recursive build.

cat module1/test/test.sh 
export SRCTEST="module1/test/testRun.c 
    module1/module1.c"
export CFLAGS="$CFLAGS -Imodule1"

cat module2/test/test.sh 
export SRCTEST="module2/test/testRun.c
          module2/module2.c"
export CFLAGS="$CFLAGS -Imodule2"

Then your Makefile could looks like:

test1:
    source module1/test/test.sh && gcc -o $@ $$CFLAGS $$SRCTEST
test2:
    source module2/test/test.sh && gcc -o $@ $$CFLAGS $$SRCTEST

Also you can do something with include instruction. Redefinition could be avoided by checking the build target, but this is not a good way.

Answer 2

Your examples are not clear enough for us to answer.

For one thing, tt's not clear how the name of the test executable is related to the name of the module. Is it really the case that the modules end with a number and the generated test program should also end with that same number ( Module1 -> test1 )? Or is there some other relationship? There doesn't appear to be any variable containing a test name in the test.mk file so how is the test name computed?.

Second, it will make your life very difficult if you redefine the same variables in every test.mk file. There is no "scoping" in make that will allow you to say "this instance of CFLAGS is used only for this included makefile". Each time you include a different test.mk file it will overwrite the previous settings.

It CAN be done: you'll need to use a combination of define variables to hold rule definitions, then eval to evaluate the rules.

Let's suppose that you added a new variable to test.mk which defined the test name, and you qualified your variables with this name as well; then your life is much easier:

Module1/test/test.mk would contain:

TESTNAME = test1
test1_SRCTEST = module1/test/testRun.c \
                module1/module1.c
test1_CFLAGS = -Imodule1

Now in your main makefile you would create a variable holding the rule you wanted to define:

define MAKETEST
include $T
$$(OUTDIR)/$$(TESTNAME): $$(OUTDIR)/% : $$($$(TESTNAME)_SRCTEST)
        $$(CC) $$(CPPFLAGS) $$(CFLAGS) $$($$*_CFLAGS) -o $$@ $$^
endef

$(foreach T,$(DIRTEST),$(eval $(MAKETEST)))

Note, this is untested.