Makefile 中的问题 C LINUX

Question

I have the following files in a folder:

main.c | file1.c | file1.h | file2.c | file2.h

main.c is dependent on file1.h and file2.h. However, file1.c is also dependent on file2.h, and this is my problem.

Here's what I have:

CC = gcc
CFLAGS = -Wall -g

BIN = main


all: $(BIN)


main: main.o file1.o file2.o
    $(CC) -o $@ $^

main.o: main.c file1.h
    $(CC) $(CFLAGS) -c -o $@ $<

file1.o: file1.c file1.h
    $(CC) $(CFLAGS) -c -o $@ $<

file2.o: file1.c file1.h
    $(CC) $(CFLAGS) -c -o $@ $<

clean:
    rm -f *.o $(BIN)

Obviously this doesn't work.

What can I do to make my makefile work? And to improve it?

EDIT:

In main.c:

#include "file1.h"

In file1.c:

#include "file1.h"

In file1.h:

#include "file2.h"

In file2.c:

#include "file2.h"

I have no includes in file2.h.

Am I doing this right?

Answer 1

Just add file2.h as a dependency of file1.o

It should work.

Answer 2

I suggest using make 's wildcard matching. For the demonstration, I filled the files with some simple functions.

file2.h

void func2(void);

file2.c

#include "file2.h"

void func2()
{
        return;
}

file1.h

#include "file2.h"

void func1();

file1.c

#include "file1.h"

void func1()
{
        func2();
        return;
}

main.c

#include "file1.h"

int main()
{
        func1();
        return 0;
}

Now, you can use make 's wildcard matching, Ex, *.o: *.c for producing .o file from any .c file.

Makefile

CC = gcc
CFLAGS = -Wall -g
OBJS = main.o file1.o file2.o
BIN = main

all : $(BIN)

main: $(OBJS)
        $(CC) $(CFLAGS) -o $@ $^

*.o : *.c
        $(CC) $(CFLAGS) -c -o $@ $^
clean:
        rm -f *.o $(BIN)

Terminal Session

$ ls 
file1.c  file1.h  file2.c  file2.h  main.c  Makefile
$ make 
gcc -Wall -g   -c -o main.o main.c
gcc -Wall -g   -c -o file1.o file1.c
gcc -Wall -g   -c -o file2.o file2.c
gcc -Wall -g -o main main.o file1.o file2.o
$ ./main
$ make clean 
rm -f *.o main
$ ls 
file1.c  file1.h  file2.c  file2.h  main.c  Makefile

In general, it is advised to keep .h files separately, Ex, having includes directory. With that modification, Makefile becomes

Makefile

CC = gcc
CFLAGS = -Wall -g -I./includes
OBJS = main.o file1.o file2.o

main: $(OBJS)
        $(CC) $(CFLAGS) -o $@ $^

*.o : *.c
        $(CC) $(CFLAGS) -c -o $@ $^
clean:
        rm -f *.o $(BIN)

Terminal Session

$ ls 
file1.c  file2.c  includes  main.c  Makefile
$ ls includes/
file1.h  file2.h
$ make 
gcc -Wall -g -I./includes   -c -o main.o main.c
gcc -Wall -g -I./includes   -c -o file1.o file1.c
gcc -Wall -g -I./includes   -c -o file2.o file2.c
gcc -Wall -g -I./includes -o main main.o file1.o file2.o
$ ./main 
$ make clean 
rm -f *.o main
$ ls
file1.c  file2.c  includes  main.c  Makefile