[英]Cross-compilng C program for ARMv8-A in Linux X86_64 system
I am new to ARM architecture,I am experimenting with cache clean of Arm.我是 ARM 架构的新手,我正在试验 Arm 的缓存清理。
I am following "Programmer's Guide for ARMv8-A" since Gem-5 has this implementation as per ( https://www.gem5.org/documentation/general_docs/architecture_support/arm_implementation/ ),我正在关注“ARMv8-A 程序员指南”,因为 Gem-5 根据( https://www.gem5.org/documentation/general_docs/architecture_support/arm_implementation/ )具有此实现,
I am trying to cross-compile below code in linux x86_64 system using arm-linux-gnueabi-gcc test_arm.c -o test , but I am getting following error.我正在尝试使用arm-linux-gnueabi-gcc test_arm.c -o test在 linux x86_64 系统中交叉编译以下代码,但出现以下错误。
/tmp/ccTM2bcE.s: Assembler messages:
/tmp/ccTM2bcE.s:38: Error: selected processor does not support requested special purpose register -- `mrs r3,ctr_el0'
/tmp/ccTM2bcE.s:69: Error: bad instruction `dc cavu,r3'
/tmp/ccTM2bcE.s:150: Error: selected processor does not support `dsb ish' in ARM mode
/tmp/ccTM2bcE.s:159: Error: selected processor does not support `dsb ish' in ARM mode
code代码
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <unistd.h>
#include <stdint.h>
void clean_invalidate(uint64_t addr){
uint64_t ctr_el0 = 0;
if(ctr_el0 == 0)
asm volatile("mrs %0, ctr_el0":"=r"(ctr_el0)::);
const size_t dcache_line_size = 4 << ((ctr_el0 >>16)&15);
addr = addr & ~(dcache_line_size - 1);
asm volatile("dc cvau, %0"::"r"(addr):);
}
int main(){
int a[1000];
int index = 0;
uint64_t addr = 0;
double time_spend = 0.0;
clock_t begin = clock();
for(int i=0;i<100;i++){
index = rand()%1000;
a[index] = index;
addr = (uint64_t)(&a[index]);
asm volatile("dsb ish");
clean_invalidate(addr);
asm volatile("dsb ish");
int b = a[index];
}
clock_t end = clock();
time_spend = (double)(end-begin)/CLOCKS_PER_SEC;
printf("Time:%f\n",time_spend);
return 0;
}
Can someone please help me to compile this code for ARMv8-A in Linux X86 system.有人可以帮我在 Linux X86 系统中为 ARMv8-A 编译此代码。
PS: You can ignore the cast from pointer to integer of different size warning. PS:您可以忽略从指针到 integer 的不同大小警告的强制转换。
I think mrs %0,ctr_el0
is an ARMv8 aarch64 instruction, and arm-linux-gnueabi-gcc
is the armv7/aarch32 compiler, you have to use aarch64-linux-gnu-gcc
.我认为
mrs %0,ctr_el0
是 ARMv8 aarch64 指令,而arm-linux-gnueabi-gcc
是 armv7/aarch32 编译器,你必须使用aarch64-linux-gnu-gcc
。
And dc cavu
does not seem to exist, did you mean dc cvau
?而且
dc cavu
似乎不存在,您的意思是dc cvau
吗?
With those two changes it compiles.通过这两个更改,它可以编译。
To be honest, there is also MRS in ARMv7 in addition to MRC, but I haven't fully understood when each one should be used in there.老实说,ARMv7中除了MRC之外还有MRS,但是我还没有完全明白什么时候应该在里面使用它们。 aarch64 has only MRS so it's simpler.
aarch64 只有 MRS,所以更简单。
For the specific case of CTR_EL0, there exists an analogous aarch32 register CTR, but that one is accessed with MRC according to the manual, not MRS.对于 CTR_EL0 的具体情况,存在一个类似的 aarch32 寄存器 CTR,但根据手册使用 MRC 访问,而不是 MRS。
Here are a gazillion runnable examples that might be of interest as well:以下是可能感兴趣的大量可运行示例:
The problem comes with the instruction: asm volatile("mrs %0, ctr_el0":"=r"(ctr_el0)::);问题来自指令: asm volatile("mrs %0, ctr_el0":"=r"(ctr_el0)::);
which is translated to an assembler instruction, it is tie to your ARM architecture, for this you should take a look into your correspondign arm registers and see if it is included there, If not, then you need to find another register with a similar purpose它被翻译成汇编指令,它与您的 ARM 架构相关,为此您应该查看您对应的 arm 寄存器,看看它是否包含在那里,如果没有,那么您需要找到另一个具有类似目的的寄存器
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