[英]Error (10170): Verilog HDL syntax error at CRC_configurable.v(62) near text: "integer"; expecting "end"
I'm working with Quartus Prime Lite Edition and having a case
statement with:我正在使用 Quartus Prime Lite Edition 并有一个
case
声明:
S2: begin
dat[WID_DAT-1 :1] <= dat[WID_DAT-2 :0];
dat[0] <= 0;
crc[0] <= crc_temp[0];
integer i;
for (i = 1; i < WID_CRC; i = i+1) begin
crc[i] <= crc_temp[i] ^ crc[i-1];
end
if(count != 0) begin
r_ns <= S2;
count <= count -1;
end
else begin
r_ns <= S_DONE;
done <= 1;
end
end
and get the error message when I Start Anlysis & Elaboration:并在我开始分析和细化时收到错误消息:
Error (10170): Verilog HDL syntax error at CRC_configurable.v(62) near text: "integer";
错误 (10170): CRC_configurable.v(62) 附近文本的 Verilog HDL 语法错误:“整数”; expecting "end".
期待“结束”。
Why is this so, and how should I avoid it?为什么会这样,我应该如何避免它?
You must not declare an integer
in the middle of a begin/end
block.您不得在
begin/end
块的中间声明integer
。 You could move the integer
declaration line outside of the always
block (before it).您可以将
integer
声明行移到always
块之外(在它之前)。
integer i;
always ...
...
S2: begin
dat[WID_DAT-1 :1] <= dat[WID_DAT-2 :0];
dat[0] <= 0;
crc[0] <= crc_temp[0];
for (i = 1; i < WID_CRC; i = i+1) begin
crc[i] <= crc_temp[i] ^ crc[i-1];
end
Or, if you give your begin block a name, you should be able to declare the integer
immediately after the begin
line.或者,如果你给你的开始块一个名字,你应该能够在
begin
行之后立即声明integer
。
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