理解 Makefile 规则

Question

I have been debugging a linking error for specific target (android), for all other targets, build is successful.

Error is something like

Test.cpp:29:57: fatal error: linux/ethtool.h: No such file or directory compilation terminated.
make: *** [../../../makefiles/rules.makefile:1012: android-arm-r/Test.o] Error 1

and build command is:

make DEBUG=no TARGET=android

I checked this rules.makefile's 1012 line:

$(OBJDIR)/%.$(OBJ_SUFFIX): %.cpp $(OBJDIR)/%.d 
     @$(cpp_PRECOMPILE) 
     $(cpp_COMMAND) $< 
     @$(cpp_POSTCOMPILE)

Now, as typical make rule pattern, I can understand that,

• TARGET is $(OBJDIR)/%.$(OBJ_SUFFIX)

• PREREQUISITES are %.cpp $(OBJDIR)/%.d (Source files, which would be mostly Test.cpp, being the only cpp file in that dir)

• RECIPE is

   @$(cpp_PRECOMPILE) $(cpp_COMMAND) $< @$(cpp_POSTCOMPILE)

Here, looking at other files, I could see,

cpp_PRECOMPILE is :
cpp_COMMAND is gcc -x c++
cpp_PRECOMPILE is :

So that makes the RECIPE, somewhat like:

     @: 
     /opt/android-arm-r9/bin/arm-linux-androideabi- gcc -x c++ $< 
     @:

Now, I am not able to understand:

1. What is @$ for?

2. $< is automatic variable holding prerequisite name. But overall what action this recipe is trying to do?

3. When no TARGET is given (default is linux)

    make CPU=x86_64 DEBUG=no

   works perfectly.

   But when TARGET=android , it fails.

    make CPU=x86_64 DEBUG=no TARGET=android

Answer 1

"@" simply silence the current line.

The "-x" option determines the language, thus $(gcc -x c++) $< compiles the file (prerequisite) as C++ file.

Answer 2

1. What is @$ for?

@$ is not a unit. The @ is a prefix that suppresses the command's output from being forwarded to make 's output. The $ is the beginning of a variable reference ( $(cpp_PRECOMPILE) ) which expands to a command to run.

2. $< is automatic variable holding prerequisite name. But overall what action this recipe is trying to do?

More specifically, $< expands to the name of the first prerequisite. This matters in your case, since the rule designates multiple prerequisites.

The variable names appearing in the recipe give a pretty clear indication of what the recipe is supposed to do:

1. $(cpp_PRECOMPILE) -- some kind of step preparing for compilation. That might be anything or nothing; it presumably depends on values of other variables, and maybe on other factors as well.

2. $(cpp_COMMAND) $< -- compile the source file named by the first prerequisite. Presumably with a C++ compiler.

3. $(cpp_POSTCOMPILE) -- some kind of post-processing, cleanup, or followup step to be performed after compilation. As with the pre-compile step, that could be anything or nothing, with the details depending on other parts of the makefile.

3. When no TARGET is given (default is linux)

    make CPU=x86_64 DEBUG=no

   works perfectly.

   But when target=android, it fails.

    make CPU=x86_64 DEBUG=no TARGET=android

TARGET (and DEBUG and CPU ) are details specific to your particular makefile, not features of make generally. We can't speak to the specifics of their effects. However, these error messages ...

 Test.cpp:29:57: fatal error: linux/ethtool.h: No such file or directory compilation terminated. make: *** [../../../makefiles/rules.makefile:1012: android-arm-r/Test.o] Error 1

... present a reasonably clear picture of what the immediate problem is: file Test.cpp , as it is being compiled, attempts to #include a C header file linux/ethtool.h , which file is not found in the cross environment supporting your cross build. That the error does not manifest when you perform a different kind of build is not particularly relevant.

You should review the build requirements documentation for the project. It may specify particular required packages, which, for a cross build such as you are trying to perform, would probably need to be installed in the cross environment. Possibly kernel headers. You may also want to seek assistance from the maintainers of the project.