每 n 个时钟周期递增一次 mod 计数器

Question

This is the verilog code for mod 64 counter, incrementing every clock cycle

module modulus64counter
#(parameter N=64,
parameter WIDTH=5)
(input clk,
input rstn,
output reg[WIDTH-1:0] out);
integer i;
always @(posedge clk) begin
if(!rstn) begin
out<=0;
end
else begin
if(out==N-1)
out<=0;
else 
out<= out+1;
end
end
endmodule

and the test bench is

module modulus64countertb;

    // Inputs
    reg clk;
    reg rstn;

    // Outputs
    wire [4:0] out;

    // Instantiate the Unit Under Test (UUT)
    modulus64counter uut (
        .clk(clk), 
        .rstn(rstn), 
        .out(out)
    );
    always #10 clk = ~clk;
    initial begin
        // Initialize Inputs
        clk = 1;
        rstn = 0;

        $monitor ("T=%0t rstn=%0b out=0X%h", $time,rstn,out);
repeat(2) @(posedge clk);
rstn <=1;
repeat(50) @(posedge clk);
$finish;
end
endmodule

Now if i want to increment the value of out every "n" clock cycle instead of consecutive clock cycle, how can i modify the program

Kindly help

Answer 1

The code below should work for you. You can always swap the out and actual_out if you insist on using out as the final counting variable.

Also, removing the out on the monitor line in the testbench will only print the value when it reaches mod n . I kept both out and actual_out on testbench's monitor to ease debugging purpose.

Verilog code

module modulus64counter #(
    parameter               N=64,
    parameter               WIDTH=8
)(
    input                   clk,
    input                   rstn,
    output reg[WIDTH-1:0]   out,
    output reg[WIDTH-1:0]   actual_out
);
    integer                 i;
    reg       [WIDTH-1:0]   cntr;
    
    always @(posedge clk) begin
        if(!rstn) begin
            out <= 0;
            actual_out <= 0;
        end else if(out == N-1) begin
            out <= 0;
            actual_out <= actual_out + 1;
        end else begin
            out <= out + 1;
        end
    end
endmodule

Testbench

module modulus64countertb;

    // Inputs
    reg         clk;
    reg         rstn;

    // Outputs
    wire [7:0]  out;
    wire [7:0]  actual_out;

    // Instantiate the Unit Under Test (UUT)
    modulus64counter uut (
        .clk(clk), 
        .rstn(rstn), 
        .out(out),
        .actual_out(actual_out)
    );
  
    always #10 clk = ~clk;
    initial begin
        // Initialize Inputs
        clk  = 1;
        rstn = 0;

        $monitor ("T=%0t rstn=%0b out=%d actual_out=%d", $time,rstn,out,actual_out);
        repeat(2) @(posedge clk);
        rstn <=1;
        repeat(200) @(posedge clk);
        $finish;
    end
endmodule

Output result simulated using edaplayground :