简体   繁体   English

如何用 Chisel Scala 语言为异步电路编写 Muller C 元素?

[英]How to write a Muller C Element in Chisel Scala Language for async circuit?

When I wrote this :当我写这个时:


class MullerC(val WIDTH: Int = 2) extends Module {
  val io = IO(new Bundle {
    val in = Input(Vec(WIDTH, Bool()))
    val out = Output(Bool())
  })

  io.out := false.B
  when (io.in.reduce(_ & _)) {
    io.out := true.B
  }.elsewhen (io.in.map(!_).reduce(_ & _)) {
    io.out := false.B
  }
}

I got Verilog like this :我得到了这样的 Verilog:

module MullerC(
  input   clock,
  input   reset,
  input   io_in_0,
  input   io_in_1,
  output  io_out
);
  assign io_out = io_in_0 & io_in_1;
endmodule

That is a simple and gate instead of a C gate.那是一个简单的和门,而不是一个 C 门。

But when I tried to add otherwise like this :但是当我尝试像这样添加otherwise内容时:


class MullerC(val WIDTH: Int = 2) extends Module {
  val io = IO(new Bundle {
    val in = Input(Vec(WIDTH, Bool()))
    val out = Output(Bool())
  })

  io.out := false.B
  when (io.in.reduce(_ & _)) {
    io.out := true.B
  }.elsewhen (io.in.map(!_).reduce(_ & _)) {
    io.out := false.B
  }.otherwise {
    io.out := io.out
  }
}

It could not be compiled any more:它无法再编译:

Exception in thread "main" firrtl.transforms.CheckCombLoops$CombLoopException: : [module MullerC] Combinational loop detected:
MullerC.io_out
MullerC._GEN_0   @[----.scala 14:38 ----.scala 15:12 ----.scala 17:12]
MullerC._GEN_1   @[----.scala 12:30 ----.scala 13:12]
MullerC.io_out  

How should I implement the Muller C in Chisel?我应该如何在 Chisel 中实现 Muller C? Many thanks.非常感谢。

I found the answer via this link: Disable FIRRTL pass that checks for combinational loops我通过这个链接找到了答案: 禁用检查组合循环的 FIRRTL pass

I should use otherwise and then add --no-check-comb-loops as a parameter to emit verilog code.我应该使用otherwise方法,然后添加--no-check-comb-loops作为参数以发出 verilog 代码。 Thanks.谢谢。

By the way, I also tried this and it works as well.顺便说一句,我也试过这个,它也有效。

class MullerC(val WIDTH: Int = 2) extends Module {
  val io = IO(new Bundle {
    val in = Input(Vec(WIDTH, Bool()))
    val out = Output(Bool())
  })

  io.out := false.B
  val allTrue = Wire(Bool())
  val allFalse = Wire(Bool())

  allTrue := io.in.reduce(_ & _);
  allFalse := io.in.map(!_).reduce(_ & _)
  io.out := Mux(allTrue | allFalse, Mux(allTrue, true.B, false.B), io.out)
}

This will generate more beautiful verilog code althought it does not matter.这将生成更漂亮的 verilog 代码,尽管这并不重要。

声明:本站的技术帖子网页,遵循CC BY-SA 4.0协议,如果您需要转载,请注明本站网址或者原文地址。任何问题请咨询:yoyou2525@163.com.

 
粤ICP备18138465号  © 2020-2024 STACKOOM.COM