[英]Help understanding DIV instruction in x86 inline assembly
While reading through some source code in a GNU project, I came across this bit of inline assembly: 在阅读GNU项目中的一些源代码时,我遇到了一些内联汇编:
__asm__ (
"divq %4"
: "=a" (q), "=d" (r)
: "0" (n0), "1" (n1), "rm" (d)
);
Here the variables q
, r
, n0
, n1
, and d
are 64-bit integers. 这里变量q
, r
, n0
, n1
和d
是64位整数。 I know enough assembly to get the gist of what this does, but there's some details I'm not certain about. 我知道足够的装配来得到它的作用,但有一些我不确定的细节。
What I understand: 我的理解:
We're dividing the contents of the RAX register by d
, placing the quotient in q
, and placing the remainder in r
. 我们将RAX寄存器的内容除以d
,将商置于q
,并将余数放在r
。
What I don't understand 我不明白
In the input operands specification: 在输入操作数规范中:
: "0" (n0), "1" (n1), "rm" (d)
registers "0" and "1" are forced to rax
and rdx
because of the output specification: 由于输出规范,寄存器“0”和“1”被强制为rax
和rdx
:
: "=a" (q), "=d" (r)
And the div
instruction family wants the numerator in RDX:RAX
. div
指令族想要RDX:RAX
的分子RDX:RAX
。 The divisor can be in a general purpose register (not otherwise used - ie., not RAX
or RDX
) or memory, which is specified by the "rm" constraint. 除数可以在通用寄存器中(不是以其他方式使用 - 即,不是RAX
或RDX
)或由“rm”约束指定的存储器。 Registers RDX
, RAX
, and the divisor operand make up the 3 inputs. 寄存器RDX
, RAX
和除数操作数组成3个输入。
So this will end up performing the division: n1:n0 / d
where n1:n0
is a quantity loaded into rdx:rax
. 所以这将最终执行除法: n1:n0 / d
其中n1:n0
是加载到rdx:rax
的数量。
As you correctly observe the div
family works on the fixed registers a
and d
, rax
and rdx
for divq
. 正确地观察div
系列工作在固定寄存器a
和d
, rax
和rdx
for divq
。 The a
register gets its input from n0
which is aliased to the 0th register, namely a
. a
寄存器从n0
获得输入, n0
是第0寄存器的别名,即a
。 n1
is a dummy input aliased to d
, probably just to ensure that this register is not used for other purposes. n1
是一个别名为d
的伪输入,可能只是为了确保该寄存器不用于其他目的。
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