在SystemC中处理sc_logic值时出现问题

Question

I'm writing an application in order to simulate a hardware system using SystemC libraries. My problem is handling the sc_logic type. Consider a simple module

SC_MODULE(MyModule) {
   sc_in_clk clk;
   sc_out<sc_logic> outsig;
   void main_process();
   SC_CTOR(MyModule) {
      SC_METHOD(main_process);
      sensitive << clk;
   }
};

Consider the implementation of the process:

void MyModule::main_process() {
   this->outsig.write(SC_LOGIC_1);
}

OK. Problem: outsig is always '0' and never changes its value. I write many signals in my simulation but this problem occurs only with sc_logic values in sc_out ports.

Can anybody help me?

Answer 1

将sensitive << clk放在构造函数中的SC_METHOD 之前 。